Description

This block implements sixteen (16) capacitor differential equations. The FPGA resources used for the computation of the solution of these differential equations is shared between all sixteen capacitors.

Mask Parameters

Configuration tab

Controller name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Number of capacitors: This parameter sets the maximum number of capacitors controlled by this block.

Sample Time: This parameter should be equal to the sample time of the capacitor differential equation solver. The solver synchronization is in slave mode, and must be controlled by an external device (e.g. an eHS solver). Refer to the firmware documentation to know how to set this parameter.

LoadIn port number: This parameter should reflect the communication port used to communicate data between the real-time model and the hardware solver via the PCIe link. Refer to the firmware documentation to know how to set this parameter.

Capacitor parameters

Capacitance (F): This parameter sets the capacitance of the capacitors, in farads. It is set independently for each capacitor.

Capacitor initial voltage (V): This parameter sets the initial voltage across the capacitors, in volts. It is set independently for each capacitor.

Current Input Selection (1 .. 16): This parameter is used to select which signal must be used as the capacitor current input of the differential equation solver. It is set independently for each capacitor. Refer to the firmware documentation to know the list of signals available for this parameter, and their index.

Inputs

This block has no input.

Outputs

Status: This output is the output status of the LoadIn function used within the block. Refer to the LoadIn block help for more information about the interpretation of this status code.

Characteristics and limitations

The differential equation is solved using the backward-Euler integration technique, that is Vc(n) = Vc(n-1)+Ic(n-1)*Ts/C.

Sample time: The block minimum sample time is 85 ns. The computation total latency is 180 ns.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.