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Etienne Leduc

Sylvain Ménard

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Model name

3-phase 2-level back-to-back converter

Model diagram

Image Removed
Image Added

Inputs (sources)

6

Switches

12

Outputs (measurements)

6

States (L, C, ...)

7

Hardware

OP4810-IO

  • FPGA:

 Xilinx 

  •  Xilinx Versal VM1302

Software

  • Platform: RT-LAB or HYPERSIM

Minimum license required

eHSx16

Minimum time-step

eHSx16 Standard: 300 ns

eHS High Performance: 95 ns