The OP5707-IO expansion unit was designed with the Xilinx® VC707 Virtex®-7 485T FPGA to provide additional signal conditioning to OPAL-RT simulators.
The FPGA is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations.
It can be programmed via the MUlti-System Expansion link (MuSE).

The combination of this high-end FPGA, with a high number of I/O lines (up to 256), and high-speed connectivity for communication with the OPAL-RT simulator and with third-party units under test (UUT), makes the OP5707-IO perfectly suited to complex or I/O intensive simulations.

Features 

• Xilinx® Virtex®-7 485T FPGA technology:
  • Programmed via MuSE
  • The FPGA is used to execute models designed with the OPAL-RT RT-XSG tool, manage the I/O lines and execute embedded FPGA-based simulations.
  • It exchanges data with the real-time simulations running on the target computer CPUs via MuSE.
• Capable of controlling any combination of up to eight OP5300 Mezzanine Modules (analog or digital)
  • Each module controls 16 or 32 lines for a total of up to 256 I/O.
• 16 SFP ports for high-speed communication between FPGA-based systems or external devices

...