The OP5707-IO expansion unit was designed with the Xilinx® VC707 Virtex®-7 485T FPGA to provide additional signal conditioning to OPAL-RT simulators. The FPGA is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations. It can be programmed via the MUlti-System Expansion link (MuSE).
The combination of this high-end FPGA, with a high number of I/O lines (up to 256), and high-speed connectivity for communication with the OPAL-RT simulator and with third-party units under test (UUT), makes the OP5707-IO perfectly suited to complex or I/O intensive simulations.
Xilinx®Virtex®-7 485T FPGA technology:
Programmed via MuSE
The FPGA is used to execute models designed with the OPAL-RT RT-XSG tool, manage the I/O lines and execute embedded FPGA-based simulations.
It exchanges data with the real-time simulations running on the target computer CPUs via MuSE.
Each module controls 16 or 32 lines for a total of up to 256 I/O.
16 SFP ports for high-speed communication between FPGA-based systems or external devices
The figure below shows a block diagram showing the architecture of the OP5707-IO Expansion Unit linked to a simulator acting as the primary device. By default, the communication link is using MuSE via one SFP socket (illustrated in the block diagram below). Other free SFP sockets can be used to connect other devices. Optional communication links are available (see next section).
Communication with the Master Unit
The OP5707-IO can communicate with the simulator (or master unit) in three different ways:
Using SFP socket (default communication mean), see the section above.
Using optionalDolphin SW-Link PCIe adapter (low profile)
Using optionalOneStop PCIe Target Cable Adapter (low profile)
The figure below shows a block diagram showing the architecture of the OP5707-IO Expansion Unit linked to a simulator acting as the primary device using Dolphin or OneStop PCIe adapter. To communicate, both the simulator and the I/O expansion unit must have the same PCIe adapter card.
Optional Dolphin SW-Link PCIe adapter and OneStop PCIe Target Cable Adapter must be ordered at the purchase of the unit. Each card must be factory installed in a PCIe slot at the back of the chassis. Cables are sold separately.
The sixteen SFP sockets allow interconnection with other OPAL-RT chassis or external devices, like amplifiers or MMC controllers. The standard communication protocols available with the OP5707-IO are based on Xilinx Aurora (1 to 5 Gbps).
There are two standard modes of operation available for the SFP ports, both based on the Xilinx Aurora communication protocol:
Generic Aurora communication: this mode is enabled using the Generic Aurora blocks of the OPAL-RT RT-XSG toolbox.
These blocks are used to exchange data with third-party devices or with other OPAL-RT systems.
The data communication layer (data packing/unpacking) must be configured by the user according to the targeted application.
The communication speed is configurable between 1 and 5 Gbps and the SFP transceivers must be selected accordingly.
The communication speed is set to 5Gbps by default, but downgrades automatically to the speed of the other port, if that port is used at a lower speed for third-party device connection.
Only one SFP is used for the MuSE link, the other SFP ports remain available for the legacy Generic Aurora link.
Other protocols like the Gigabit Ethernet can also be implemented.
The MuSE link is compatible with OPAL-RT Boards and OPAL-RT’s new I/O management software architecture. Restrictions to using MuSE with OPAL-RT Board software architecture may apply depending on your application and software configuration. Contact your sales representative or field application engineer to verify compatibility.
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