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Block
Mask
Description
The OpCtrl provides an interface to different Opal-RT card via the PCIe bus. The card holds a Xilinx FPGA chip and can control up to 256 I/O lines. The above pictures are showing an OpCtrl configured to control a VC707 TE0741 board, but the block can also be used to control an OP5142, ML605, OP7160, OP7161, VC707 or OP7161 boardMMPK7 board and the new OP4810 or OP4815 boards.
The card is reconfigurable with bitstreams produced using the Opal-RT RT-XSG product, version 2.2 or higher. The OpCtrl block allows the user to specify the card type and which bitstream is required by the model. Programming of the flash memory of the card is performed accordingly before model loading, using the flash_update utility.
The OpCtrl block controls the synchronization mode of the card. The synchronization unit is fully compatible with other Opal-RT hardware synchronized cards (OP5110, OP5130-XSG, etc.) and is supported by the OpConfigSync block for easy synchronization source specification in multi-cards models.
Data transfers to and from the card as well as data pre- and post- processing are not performed with the OpCtrl block, but via a block set of function blocks. Raw data transfers are performed using the DataIn Recv block (for data transfers from the card to the model) and DataOut Send block (for data transfers from the model to the card) that are also available from the 'Opal-RT/Common' library. Other functionality blocks such ad LoadIn and LoadOut are also supported.
TheOpCtrl The OpCtrl block is also used to set the simulation state on the card. During the simulation, an RT-LAB model with an Opal-RT card passes through 4 states: LOAD, PAUSE, EXECUTE and RESET. The OpCtrl block sends the current state to the card through the PCIe bus. For more information, check the Model State Example
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| Controller Name | This parameter enables the binding between this OpCtrl block and functionality blocks that must be associated with the same card. This string must be unique among all OpCtrl blocks present in the same model. |
| Board ID | This parameter is the integer value represented by the board index dip-DIP switch of the backplane adapter board to which the card is connected. The value is in the range of 0 to 31. If the card is not connected to an adapter board, the value is 0. |
| Primary Bitstream FileName | This is the name of the primary bitstream to be programmed on the board before the model is loaded. The bitstream must have been produced with RT-XSG and must be available in the model directory at load time. Please note that the name of Bitstream file name should match the board type that is selected in the "Board Type" parameter. |
| Bitstream Configuration | This is the configuration of the bitstream to be programmed on the card before the model is loaded. This parameter allows the user to use the same bitstream for several purposes. |
| Synchronization mode | This popup allows the selection of the Master, Slave or Master with external clock mode of hardware synchronization. Master mode must be used when the card is selected as the synchronization source of the model. Slave mode can be used when the synchronization source of the model is another Opal-RT card such as OP7160, OP5110, OP5130-XSG, etc. Master with external clock mode must be used when the OpCtrl block acts as the synchronization source but receives the RTSI signal from another device. |
| Generate External Clock | Not yet supported. |
| Decimation factor | This parameter is available only when the Slave mode of synchronization is selected. Not yet supported. |
| Sample Time (s) | This parameter allows the user to specify the sample time for this block, in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem). These synchronization rules must be respected in the model:
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| Board Type | This popup allows the selection of the board type to control. This can make the board switching process easier for the user. |
| If the Board Type selected is OP48xx, this parameter specifies: | |
| This parameter is the IP address of the Versal chassis, as shown on its LCD. |
| This parameter is the name of the chassis, as shown on its LCD. |
| Secondary used for Simulation | Specifies if other FPGA cards are used. A maximum of 8 cards per block are supported and for each card, one bitstream file is needed. This option is only available for OP7160 and OP7161 Board Types. |
| If the "Secondary used for Simulation" option is checked, this parameter specifies: | |
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| the The name of the first bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the third bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the fifth bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the seventh bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the ninth bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the eleventh bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| the The name of the thirteenth bitstream. Please note that the name of a Bitstream file name should match the board type and the slot number. |
| Synchronization type | Specifies if the synchronization is done via LVDS (audio) or optical fiber. This option is only available for the VC707 card. |
| Disable strict hardware mismatch validation | This parameter activates the use of multiple I/O card types based on general compatibility rules instead of using the exact hardware ID values. This option is only available when TE0741 or VC707 is selected as board type. |
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The Error outport returns the following error codes:
| Value | Description |
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| 0 | No error. |
| -1 | Card not detected. |
| -2 | Timeout waiting for a synchronization signal. If the block is in Slave mode, verify that the RTSI synchronization signal is properly connected. |
| -3 | Overrun detected. |
| -10 | This value can be added to the above codes. It signals a hardware mismatch error. |
The IDs outport returns the 8 hardware identification codes of the conditioning modules connected to the card via the backplane adaptor board.
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