Block

Mask

Description

The OpCtrl provides an interface to different Opal-RT card via the PCIe bus. The card holds a Xilinx FPGA chip and can control up to 256 I/O lines. The above pictures are showing an OpCtrl configured to control a TE0741 board, but the block can also be used to control an OP5142, ML605, OP7160, OP7161, VC707 or MMPK7 board and the new OP4810 or OP4815 boards.

The card is reconfigurable with bitstreams produced using the Opal-RT RT-XSG product, version 2.2 or higher. The OpCtrl block allows the user to specify the card type and which bitstream is required by the model. Programming of the flash memory of the card is performed accordingly before model loading, using the flash_update utility.

The OpCtrl block controls the synchronization mode of the card. The synchronization unit is fully compatible with other Opal-RT hardware synchronized cards (OP5110, OP5130-XSG, etc.) and is supported by the OpConfigSync block for easy synchronization source specification in multi-cards models.

Data transfers to and from the card as well as data pre- and post- processing are not performed with the OpCtrl block, but via a set of function blocks. Raw data transfers are performed using the DataIn Recv block (for data transfers from the card to the model) and DataOut Send block (for data transfers from the model to the card) that are also available from the 'Opal-RT/Common' library. Other functionality blocks such ad LoadIn and LoadOut are also supported.

The OpCtrl block is also used to set the simulation state on the card. During the simulation, an RT-LAB model with an Opal-RT card passes through 4 states: LOAD, PAUSE, EXECUTE and RESET. The OpCtrl block sends the current state to the card through the PCIe bus. For more information, check the Model State Example

Only one OpCtrl block must be found in one model for each card used in the model. In multi-subsystem models, use OpLnk blocks in other subsystems sharing the same card.

Parameters

Inputs

This block has no input.

Outputs

This block has two outputs:

The Error outport returns the following error codes:

The IDs outport returns the 8 hardware identification codes of the conditioning modules connected to the card via the backplane adaptor board.

Two identification codes are returned for each slot of the carrier backplane, one for section A and one for section B of the carrier. For example, if an analog carrier OP5220 is installed in slot 1 of the carrier backplane connected to the card, and if one OP5330 module installed in slot A of this carrier and one OP5340 module installed in slot B, the first two hardware IDs are 195 (or 'C3', in hexadecimal notation) and 193 (or 'C1'). Other typical IDs are 235 ('EB') for section A and 234 ('EA') for section B of an OP5251 digital I/O carrier. When no carrier is installed in one slot, both IDs are set to 255 ('FF').

The hardware mismatch error is set when the hardware installed in one slot does not match the hardware required by the RT-XSG bitstream for that slot.

Characteristics and Limitations

This block must be run in Hardware Synchronized mode.

Only XHP-mode is presently supported.

Please refer to the RT-XSG documentation for hardware setup.