Page Comparison

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• • <model folder>/RT-XSG Reports/Synthesis.result:
    Log of the synthesis process, during which the generated HDL code is compiled and translated into logical equations.
  • <model folder>/RT-XSG Reports/Xflow.result:
    Log of the following processes, during which the synthesized design is converted into elements specific to the targeted FPGA device. Those elements are then placed into the device and routed together according to the specific timing constraints of the target platform. Generation errors, including resource shortage or routing errors, can be found by parsing this file.
  • <compilation folder>/netlist/vivado/bitstream_generation.rpt
    Log the result of the major steps of the bitstream generation (e.g. link_design, place_design, route_design). The result of this step is the FPGA configuration file itself (*.bit or *.pdi).

• The target platform Flash memory configuration file is generated from the FPGA configuration. The Flash memory enables the device to reconfigure itself automatically after the system power-on. The format of this file is platform-dependent (*.pdi or *.bin or *.mcs);
• Configuration files are copied into the model folder.

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• the Board Type corresponding to the targeted FPGA,
• the Bitstream Filename (with .bin, .opbin or .pdi extension), and
• the Board index of the FPGA, which is a value between 0 and 255, set on the chassis by the use of dip switches. This number is used to distinguish between FPGAs of the same type connected to the same target computer.

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