Bitstream Generation

The generation of the FPGA configuration file (bitstream) is managed by the OPAL-RT FPGA Synthesis Manager block. This block is located in the RT-XSG/Tools blockset, and must always be present in an RT-XSG model, with the other mandatory blocks.

The generation is launched by first selecting the Bitstream file check-box and then clicking the Generate File button in the block graphical user interface (GUI) (see figure). The file creation may require a lot of time to complete, depending on the host computer performance, the model complexity, and the resources available in the target platform FPGA. Typical configuration file generation time ranges from thirty minutes to several hours.

In order to generate the programming file, the following steps must be performed:

• Verify the correctness of the design using the Update diagram button from the Simulink toolbar and correct the errors, if any;
• Verify all the mandatory blocks applicable are placed inside the model;
• Insert a Synthesis Manager block into your design. In this block GUI,
  • select the appropriate re-programmable platform from the list,
  • validate the hardware configuration,
  • validate the version configuration,
  • validate the options of generation within the Synthesis Manager,
  • click the Generate File button.

The following steps are performed during the configuration file generation:

• The configuration options associated with the specific target platform chosen in the OPAL-RT Synthesis Manager block are set. The System Generator block from the System Generator for the DSP toolbox library is modified with the appropriate options. Thus, any manual setting done by the user in this block is not used for the configuration file generation;
• The RT-XSG model is completed by adding dummy elements to unused inputs and output ports of the model (for example, if any interface block is not present in the original RT-XSG model);
• All required hardware cores are generated using the Coregen tool from the Vivado IP Integrator;
• The System Generator block is invoked and the Configuration file generation is performed;
• A new window is displayed, logging the ongoing process. During this step, Vivado Design Suite is called in non-project flow to perform logic synthesis, implementation (place & route), and bitstream generation.

If any error occurs during this step, the following files contain the log of the processes until the error occurs:

• • <model folder>/RT-XSG Reports/Synthesis.result:
    Log of the synthesis process, during which the generated HDL code is compiled and translated into logical equations.
  • <model folder>/RT-XSG Reports/Xflow.result:
    Log of the following processes, during which the synthesized design is converted into elements specific to the targeted FPGA device. Those elements are then placed into the device and routed together according to the specific timing constraints of the target platform. Generation errors, including resource shortage or routing errors, can be found by parsing this file.
  • <compilation folder>/netlist/vivado/bitstream_generation.rpt
    Log the result of the major steps of the bitstream generation (e.g. link_design, place_design, route_design). The result of this step is the FPGA configuration file itself (*.bit or *.pdi).

• The target platform Flash memory configuration file is generated from the FPGA configuration. The Flash memory enables the device to reconfigure itself automatically after the system power-on. The format of this file is platform-dependent (*.pdi or *.bin or *.mcs);
• Configuration files are copied into the model folder.

FPGA Configuration

Once the bitstream generation is complete, the bitstream must be loaded in the FPGA.

Direct programming of the FPGA from the Windows computer can be done by the use of the Hardware Manager tool of Vivado. A JTAG cable must then be connected between a USB port of the Windows computer and the JTAG port of the chassis where the targeted FPGA is located.

However, programming the FPGA via JTAG does not make the bitstream persistent if the chassis is reset or powered off. To overcome this limitation, the OPAL-RT software and the RT-XSG software make use of a flash memory of the FPGA board in order to store the bitstream configuration file, so it can be reloaded automatically in the FPGA at power-up.
The transfer of the bitstream to the target computer and its copy in the flash memory of the FPGA are handled by the OPAL-RT software during the Load phase of the OPAL-RT software model.

For this phase to execute properly, the following conditions must be met:

• The bitstream file and its associated configuration file must be copied to the folder of the OPAL-RT software model;
• Depending on the driver used within the OPAL-RT software, the way to indicate the FPGA type and its bitstream file may change, refer to proper documentation OpCtrl, OpalBoards, HYPERSIM).

The OpCtrl block must specify :

• the Board Type corresponding to the targeted FPGA,
• the Bitstream Filename (with .bin, .opbin or .pdi extension), and
• the Board index of the FPGA, which is a value between 0 and 255, set on the chassis by the use of dip switches. This number is used to distinguish between FPGAs of the same type connected to the same target computer.

After the bitstream file is transferred to the target computer, the tool flash_update is called by the OPAL-RT software.

This tool first sets the FPGA in programming mode by loading a bitstream called SAFE bitstream pre-stored in the FPGA during factory tests at OPAL-RT TECHNOLOGIES. When the FPGA is in SAFE mode, flash_update transfers the new configuration file to the flash memory of the FPGA. When the bitstream transfer is completed, flash_update sends a command to the FPGA so it reloads itself with the new bitstream.

Warnings or errors occurring during flash_update execution are listed in the display window of the OPAL-RT software model subsystem.

Flash programming is performed only if needed, i.e. when the bitstream specified in the OPAL-RT software model is different from the bitstream already programmed in the FPGA.