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Half-line Block Configurations
Name | Description | Unit | |
|---|---|---|---|
Half stubline model | Use inductance only or Use capacitance only, whether the half-line should be used as an inductance or a capacitance | - | |
Inductance | Inductance value when “Use inductance only” is choosen | H | |
Capacitance | Capacitance value when “Use inductance only” is choosen | F | |
Round trip latency | Communication latency for the round trip delay from HYPERSIM to eHS and back to HYPERSIM. Typically 3 times the sampling time of HYPERSIM | s | |
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Click on your firmware configuration at the bottom left of Schematic Editor.
Select or create your simulation setup. Note that all FPGA Firmware support the Half Line Model.
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Click on the Solver Settings button next to your firmware configuration button.
Define your solver settings for the simulation.
The example model in HYPERSIM is reproduced in Schematic Editor. See the figure below. The half-line has to be configured as it is done in HYPERSIM model.
IO Configuration
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Open the I/O Interface Configuration
Add an OPAL-RT Board
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Select the correct Chassis ID. This example uses an OP4610XG (Kintex-7) target.
Select Optical for the type of generated synchronization signal.
Select Standard repositories for the bitstream configuration location, then select your bitstream configuration file. In this example, the bitstream configuration file is
TE0741_41_4-EX-0001-eHSx128_Gen4MachinesIOConfig2.opal
And the bitstream name is
TE0741_4-EX-0001-3_5_0_817-eHSx128_Gen4_Machines_IOConfig2-3C-17.bin
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Simulation and Results
The simulation has been executed and results have been recorded. The figure below presents currents from the main voltage source to the different lines, respectively from Reference (without decoupling elements displayed in red), CPU (displayed in blue) and eHS (displayed in green). This figure also displays the DC voltage passed the rectifier for each line, respectively again from Reference (without decoupling elements), CPU and eHS.
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