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The OP5705-IO expansion unit was designed with the Xilinx® Artix®-7 200T FPGA to provide additional inputs and outputs to OPAL-RT simulators.
The FPGA is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations.
It can be connected to OPAL-RT simulators via MUlti-System Expansion link (MuSE) or PCIe link.

The combination of this versatile FPGA, with a high number of I/O lines (up to 256), and high-speed connectivity for communication with the OPAL-RT simulator and with third-party units under test (UUT), makes the OP5705-IO perfectly suited to I/O intensive simulations.

Features 

• Xilinx® Artix®-7 200T FPGA technology:
  • Programmed via MuSE or PCIe link.
  • The FPGA is used to execute models designed with the OPAL-RT RT-XSG tool, manage the I/O lines and execute embedded FPGA-based simulations.
  • It exchanges data with the real-time simulations running on the target computer CPUs via MuSE.
• Capable of controlling any combination of up to eight OP5300 Mezzanine Modules (analog or digital)
  • Each module controls 16 or 32 lines for a total of up to 256 I/O.
• 4 SFP ports for high-speed communication between FPGA-based systems or external devices

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