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This chapter covers important topics related to the creation of an RT-LAB Simulink model with an eHS solver. It is assumed that the user is already familiar with the RT-LAB and Simulink simulation environments.
Circuit-Under-Test Design Using the
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Simscape Electrical Specialized Power Systems (SPS) Simulink Toolbox
Circuit Design Using the
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SPS Libraries
The circuit must be designed using a special subset of blocks found in the SimPowerSystems Simscape Electrical Specialized Power Systems (SPS) libraries.
Also, these blocks must be properly named such that they can be easily managed outside the eHS solver.
Supported Blocks
In the SimPowerSystems SPS Elements library, the following blocks are supported (refer to Figure 2):
Series RLC Branch/Load
Parallel RLC Branch/Load
Ground/Neutral
Breaker
Pi section lines
Linear Transformers
Mutual Inductances
Inductance Matrix Type Transformers
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In the SimPowerSystems SPS Measurements block library, the following blocks are supported (refer to Figure 3):
Current Measurement
Voltage Measurement
Three-Phase VI Measurement
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In the SimPowerSystems SPS Power Electronics block library, the following blocks are supported (refer to Figure 4):
Breaker
Diode
IGBT
IGBT/Diode
Ideal Switch
Three-Level Bridge
Thyristor
Universal Bridge
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In the SimPowerSystems SPS Electrical Sources block library, the following elements are supported (refer to Figure 5):
DC Voltage Source
AC Voltage Source
AC Current Source
Controlled Voltage Source
Controlled Current Source
Three-Phase Source
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Component Naming (7)
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7 This naming convention is optional when using the eHSx32 for OP4200 block. |
The algorithm implemented by OPAL-RT (to convert the SimPowerSystems SPS model into the data used by the eHS to compute the currents and voltages in the circuit in real-time) requires that the model be analyzed to find the supported elements listed above. For source and switch control signals, as well as measurement outputs, the corresponding elements are listed in alphabetical order and will be accessible in that order within the Simulink/RT-LAB environments.
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The following naming convention is strongly recommended:
Switching devices should be named with the prefix “SW” followed by a 2-digit index, starting from SW01. Elements categorized as “switching elements” are the following: Diode, IGBT/Diode, Breaker and Ideal Switch. This prefix can be followed by other characters.
Sources, whether controlled current or voltage sources, should have the prefix “U” followed by a 2-digit index, starting from U01. This prefix can be followed by other characters. To avoid confusion, the prefix for a three-phase source should contain three indices, starting with phase A (e.g. “U05 U06 U07 Vabc”).
Measurements of any kind should have the prefix “Y” followed by a 2-digit index, starting from Y01. This prefix can be followed by other characters.
Inductances, capacitors, and resistors are not accessed directly from RT-LAB and do not have any special naming convention.
Figure 6 below displays an example of a valid SimPowerSystems SPS model for a three-phase inverter:
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Circuit-Under-Test Design Using the PSIM Toolbox
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The circuit must be designed using a special subset of blocks found in the PSIM libraries. Also, these blocks must be properly named such that they can be easily managed outside the eHS solver.7
Supported Blocks
Sources
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Passive components
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Switches
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Ground
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Measurements
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Transformers
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Component Naming
The algorithm implemented by OPAL-RT (to convert the PSIM model into the data used by the eHS to compute the currents and voltages in the circuit in real time) requires that the model be analyzed to find the supported elements listed above. For source and switch control signals and measurement outputs, the corresponding elements are listed in alphabetical order and will be accessible in that order within the Simulink/RT-LAB environments. For that reason, it is strongly recommended to rename elements with names that are easily recognizable and whose identification from within RT-LAB will be straightforward.
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Below is an example of a valid PSIM model for a Three-Level NPC:
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Circuit-Under-Test Using the PLECS Blockset Simulink Toolbox
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Figure 8 shows the supported blocks from PLECS Blockset library.
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Example of Circuit Design Using PLECS
Figure 9 below demonstrates an example of a model design using the PLECS Blockset for use with the eHS.
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Inserting the Circuit into an RT-LAB Model
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The circuit described by a SimPowerSystems SPS model, PLECS Blockset model, or a PSIM design (*.psimsch) is imported using an eHS block. The different eHS blocks can be found in the eFPGAsim/eHS and Converter Models Simulink Library section.
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Figure 10 below displays the eHSx32 for OP4200 block.
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The eHSx32 for OP4200 block implements a different user interface for configuration than the eHS Gen3 block to improve usability but contains many of the same features.8 Since a different user interface was developed for the OP4200, the naming convention described in the section on Building Models with the eHS Solver is not critical.
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The figures below describe the tabs of the eHSx32 for OP4200 block:
The Circuit tab of the block allows the user to configure the Circuit Model file being simulated and the Time Step information of the solver. It also contains a table of information about the Circuit Model, including the number of Sources, number of Measurements, number of Switches, and number of States. During selection, the Circuit Model is parsed automatically, allowing the other tabs of the block to be populated with information relating to the Circuit Model.
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The Gates tab allows the user to configure the Switch Source Type & Channel for each switch (either from Digital In channel or from the CPU9), the polarity of each switch (High or Low), and the Gs value of each switch.10 By selecting CPU, the block regeneration will expose this gate as an input port to the block.
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9 In order to use the firmware’s internal PWM generators as the source of a Gate in the eHS, the PWM Generators should be configured on a Digital Out channel in RT-LAB using the OPAL-RT Board driver, a Digital In Channel should be configured in the eHS block, and a loopback will need to be made physically between the Digital Out and Digital In pins. For more details, please refer to the RT-LAB User Manual and the eFPGAsim Quickstart Guide. 10 Diodes are considered disconnected as their Source Type, Channel, and Polarity are not configurable. Only their Gs values can be edited by the user. Note that when using the two-level and three-level LCA, the Gs values need to be the same for each switch in the component. |
The Inputs tab allows the user to configure the Current and Voltage Sources used in the circuit model including the Signal Source (CPU or Constant value), as well as the parameters (used to configure the value of the Constant) of each input. By selecting CPU, the block regeneration will expose this input as an input port to the block.
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The Outputs tab allows the user to view the Measurement points configured within the Circuit Model.
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The Log tab allows the user to view debugging information on the parsing of their circuit model and the stream generation.
Please refer to the Help for the block for more details on describing the inputs and outputs of this block.
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Figure 15 below displays the eHS Gen3 block. Currently, the block supports the x32, x64, and x128 form factors.
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The INPUTS port of the eHS Gen3 block accepts a vector containing Voltage & Current Source values as defined by the Circuit Model. If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the input vector will correspond to the source index of the circuit model.11
The GATES RTE/GATES STATIC port of the eHS Gen3 block accepts a vector containing Switch control values as defined by the Circuit Model. The data type of each element can either be of type RTE (for the GATES RTE port) or Double floating-point representation (for the GATES STATIC port). If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the input vector will correspond to the source index of the Circuit Model.11
The OUTPUTS port of the eHS Gen3 block returns a vector of the Voltage and Current Measurement values as defined by the Circuit Model. If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the output vector will correspond to the measurement block index in the circuit model.11 12
For a detailed overview of this block, please refer to the Help for the block.
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11 The naming is done by alphabetical order. Therefore, if the user is using their switches inside subsystems, this will have an effect on the order. To observe the order of sources, switches, and measurements, please refer to the Infos tab of the eHS Gen3 block or the appropriate tab on the eHSx32 for OP4200 block. 12 It is to be noted that while the Dual eHS block has zero hold sampled output, the outputs of eHS gen3 block are averaged over the previous CPU time step (i.e. sum of all the FPGA core output samples during the CPU time step divided by the number of samples). |
Signal Types
The eHS solver input and output signal types, as seen from RT-LAB, are of Double Floating-Point data representation. The signals are converted within the block to single precision or extended single precision. The conversion to single precision enables the solver to run faster, but can cause discrepancies between the results obtained by the eHS and those obtained by the SimPowerSystems SPS simulation for circuits with very long time constants relative to the sample time of either solver.
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Gated signals sent using the RT-EVENTS signal type “RTE Boolean” have a time resolution higher than the RT-LAB model sample time, and are thus sampled at the eHS sample time.6
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Because of inherent communication procedures between the FPGA-based hardware and RT-LAB, a latency of two RT-LAB time steps is observed between the time when commands are sent to the eHS and when its response in the circuit can be read again in RT-LAB, as shown in 0below:
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Interconnecting Multiple eHS Solvers
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Note: A diagram of the firmware is required to be sure of the solvers interconnection settings. |
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Note: FPGA-based sinusoidal source or gating signal generators, as well as other solver interconnection patterns such as machines models, can be implemented with the help of the RT-XSG toolbox or with the help of OPAL-RT development team. |
Using the Scenario Feature
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Writing the XLS Scenario File
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Getting Started
The easiest way to write the first XLS file is to generate a template by selecting the Create an XLS template for the current netlist option from the Scenario Management tab. Users can also write the XLS file themselves. The first line, from cell B1, is reserved for RLC components declaration. The first column, from cell A2, is reserved for the scenarios declaration.
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If a scenario is impossible (wrong label or scenario number greater than the maximum number of feasible scenarios), an error will be thrown.
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Verifying that Scenarios Have Been Properly Generated
While generating the eHS configuration, a log is generated in the MATLAB command prompt to advise the user of the changes made to the netlist depending on the scenario number.
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The Loss Compensation Algorithm (LCA) Feature (eHS Gen3 Only)
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The following two topologies support the LCA feature:
The two-level arm converter
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The three-level NPC arm converter
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How to Use the LCA Feature (
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SPS Workflow)
Using LCA with a Two-Level Arm Converter
To use the LCA in the SimPowerSystems SPS environment the two-level arm converter should be replaced by the universal bridge component in the eHS circuit model.
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Note: The forward voltages and Tf / Tt parameters will be discarded during the parameter extraction. Only IGBT/Diodes and Diodes are supported in the Power Electronic device dropdown list. |
Once the circuit model has been updated with the universal bridge component, the user should rebuild the CPU-model in RT-LAB. During the eHS circuit parsing process, the universal bridge will be detected as an LCA element and the loss-compensation algorithm will be used instead of the classic switching logic.
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To use the LCA feature in the SimPowerSystems SPS environment, the three-level NPC arm converter should be replaced by the Three-Level Bridge component in the eHS circuit model.
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Note: The forward voltage parameters will be discarded during the parameter extraction. Only the IGBT/Diodes option is supported in the Power Electronic device dropdown list. |
Once the circuit model is updated with the Three-Level Bridge component, the user can rebuild the CPU-model in RT-LAB. During the eHS circuit parsing process, the Three-Level Bridge component will be detected as an LCA element and the loss-compensation algorithm will be used instead of the classic switching logic.
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