This chapter covers important topics related to the creation of an RT-LAB Simulink model with an eHS solver. It is assumed that the user is already familiar with the RT-LAB and Simulink simulation environments.

Circuit-Under-Test Design Using the Simscape Electrical Specialized Power Systems (SPS) Simulink Toolbox

Circuit Design Using the SPS Libraries

The circuit must be designed using a special subset of blocks found in the Simscape Electrical Specialized Power Systems (SPS) libraries.

Also, these blocks must be properly named such that they can be easily managed outside the eHS solver.

Supported Blocks

In the SPS Elements library, the following blocks are supported:

• Series RLC Branch/Load

• Parallel RLC Branch/Load

• Ground/Neutral

• Breaker

• Pi section lines

• Linear Transformers

• Mutual Inductances

• Inductance Matrix Type Transformers

Open

In the SPS Measurements block library, the following blocks are supported:

• Current Measurement

• Voltage Measurement

• Three-Phase VI Measurement

Open

In the SPS Power Electronics block library, the following blocks are supported:

• Breaker

• Diode

• IGBT

• IGBT/Diode

• Ideal Switch

• Three-Level Bridge

• Thyristor

• Universal Bridge

In the SPS Electrical Sources block library, the following elements are supported:

• DC Voltage Source

• AC Voltage Source

• AC Current Source

• Controlled Voltage Source

• Controlled Current Source

• Three-Phase Source

Component Naming (7)

The algorithm implemented by OPAL-RT (to convert the SPS model into the data used by the eHS to compute the currents and voltages in the circuit in real-time) requires that the model be analyzed to find the supported elements listed above. For source and switch control signals, as well as measurement outputs, the corresponding elements are listed in alphabetical order and will be accessible in that order within the Simulink/RT-LAB environments.

For that reason, it is strongly recommended to rename elements with names that are easily recognizable and whose identification from within RT-LAB will be straightforward.

The following naming convention is strongly recommended:

• Switching devices should be named with the prefix “SW” followed by a 2-digit index, starting from SW01. Elements categorized as “switching elements” are the following: Diode, IGBT/Diode, Breaker and Ideal Switch. This prefix can be followed by other characters.

• Sources, whether controlled current or voltage sources, should have the prefix “U” followed by a 2-digit index, starting from U01. This prefix can be followed by other characters. To avoid confusion, the prefix for a three-phase source should contain three indices, starting with phase A (e.g. “U05 U06 U07 Vabc”).

• Measurements of any kind should have the prefix “Y” followed by a 2-digit index, starting from Y01. This prefix can be followed by other characters.

• Inductances, capacitors, and resistors are not accessed directly from RT-LAB and do not have any special naming convention.

Figure 6 below displays an example of a valid SPS model for a three-phase inverter:

Circuit-Under-Test Design Using the PSIM Toolbox

Circuit Design Using the PSIM Libraries

The circuit must be designed using a special subset of blocks found in the PSIM libraries. Also, these blocks must be properly named such that they can be easily managed outside the eHS solver.⁷

Supported Blocks

• Sources

• Passive components

• Switches

• Ground

• Measurements

• Transformers

Component Naming

The algorithm implemented by OPAL-RT (to convert the PSIM model into the data used by the eHS to compute the currents and voltages in the circuit in real time) requires that the model be analyzed to find the supported elements listed above. For source and switch control signals and measurement outputs, the corresponding elements are listed in alphabetical order and will be accessible in that order within the Simulink/RT-LAB environments. For that reason, it is strongly recommended to rename elements with names that are easily recognizable and whose identification from within RT-LAB will be straightforward.

Switching devices should be named with the prefix "SW" followed by a 2-digit index, starting from SW01. Note that the "0" cannot be ignored. Elements categorized as "switching elements" are the following: Diode, IGBT, and Bi-directional switch.

Sources, whether controlled current or voltage sources, should have the prefix "U" followed by a 2-digit index, starting from U01. Note that the "0" cannot be ignored.

Measurements of any kind should have the prefix "Y" followed by a 2-digit index, starting from Y01 and the "0" cannot be ignored.

Inductances, capacitors, and resistors are not accessed directly from RT-LAB and do not have any special naming convention.

Below is an example of a valid PSIM model for a Three-Level NPC:

Circuit-Under-Test Using the PLECS Blockset Simulink Toolbox

Circuit Design Using the PLECS Libraries

The circuit must be designed using a special subset of blocks found in PLECS. Also, these blocks must be properly named such that they can be easily managed outside the eHS solver.⁷

Supported Components

Figure 8 shows the supported blocks from PLECS Blockset library.

Example of Circuit Design Using PLECS

Figure 9 below demonstrates an example of a model design using the PLECS Blockset for use with the eHS.

Inserting the Circuit into an RT-LAB Model

eHS Blocks

The circuit described by a SPS model, PLECS Blockset model, or a PSIM design (*.psimsch) is imported using an eHS block. The different eHS blocks can be found in the eFPGAsim/eHS and Converter Models Simulink Library section.

The eHS blocks implement the driver that manages all the communication within the eHS firmware including solver initialization and the transmission in real-time of the circuit control signals (current and voltage source control signals, switching information of the transistors, breakers, and other switches).

The block must be placed in an RT-LAB compatible model that will be compiled and executed by the RT-LAB software. Templates are provided in the eFPGAsim installation (path: C:\OPAL-RT\EFPGASIM\<version>\Examples\eHS_withIOs\<chassis>\Simulink\rtlab). If your chassis is not listed, please contact OPAL-RT Support for more information about the supported hardware configuration.

The eHSx32 Gen3 Block for the OP4200

Figure 10 below displays the eHSx32 for OP4200 block.

The eHSx32 for OP4200 block implements a different user interface for configuration than the eHS Gen3 block to improve usability but contains many of the same features.8 Since a different user interface was developed for the OP4200, the naming convention described in the section on Building Models with the eHS Solver is not critical.

The Average and Downsample outputs of the block are returned as vectors containing the measurements of the Circuit Model (see below for information on the Outputs). The order of the elements is defined in the Outputs tab.

The figures below describe the tabs of the eHSx32 for OP4200 block:

• The Circuit tab of the block allows the user to configure the Circuit Model file being simulated and the Time Step information of the solver. It also contains a table of information about the Circuit Model, including the number of Sources, number of Measurements, number of Switches, and number of States. During selection, the Circuit Model is parsed automatically, allowing the other tabs of the block to be populated with information relating to the Circuit Model.

• The Gates tab allows the user to configure the Switch Source Type & Channel for each switch (either from Digital In channel or from the CPU⁹), the polarity of each switch (High or Low), and the Gs value of each switch.¹⁰ By selecting CPU, the block regeneration will expose this gate as an input port to the block.

• The Inputs tab allows the user to configure the Current and Voltage Sources used in the circuit model including the Signal Source (CPU or Constant value), as well as the parameters (used to configure the value of the Constant) of each input. By selecting CPU, the block regeneration will expose this input as an input port to the block.

• The Outputs tab allows the user to view the Measurement points configured within the Circuit Model.

• The Log tab allows the user to view debugging information on the parsing of their circuit model and the stream generation.

Please refer to the Help for the block for more details on describing the inputs and outputs of this block.

The eHS Gen3 Block

Figure 15 below displays the eHS Gen3 block. Currently, the block supports the x32, x64, and x128 form factors.

• The INPUTS port of the eHS Gen3 block accepts a vector containing Voltage & Current Source values as defined by the Circuit Model. If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the input vector will correspond to the source index of the circuit model.¹¹

• The GATES RTE/GATES STATIC port of the eHS Gen3 block accepts a vector containing Switch control values as defined by the Circuit Model. The data type of each element can either be of type RTE (for the GATES RTE port) or Double floating-point representation (for the GATES STATIC port). If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the input vector will correspond to the source index of the Circuit Model.¹¹

• The OUTPUTS port of the eHS Gen3 block returns a vector of the Voltage and Current Measurement values as defined by the Circuit Model. If the naming convention described in Figure 6 was used in the circuit model, the index of each element in the output vector will correspond to the measurement block index in the circuit model.^{11 12}

For a detailed overview of this block, please refer to the Help for the block.

Signal Types

The eHS solver input and output signal types, as seen from RT-LAB, are of Double Floating-Point data representation. The signals are converted within the block to single precision or extended single precision. The conversion to single precision enables the solver to run faster, but can cause discrepancies between the results obtained by the eHS and those obtained by the SPS simulation for circuits with very long time constants relative to the sample time of either solver.

Offline Simulation

The eHS block does not enable offline simulation. For offline simulation, the appropriate block in the eFPGAsim eHS and Converter Models Simulink Library must be used.

This block enables the developer to connect the block exactly as it is connected inside the FPGA-based board firmware (e.g. to a plant model) for more accurate results.

One offline block should be added for each solver implemented. Connections between them and any other component present in the firmware model should be done manually by the developer. This also enables the developer to simulate each part of the circuit with the appropriate sample time, especially the faster-running eHS solver.

Understanding Sample Times

The eHS solver sample time is accessed through a parameter of the eHS block. By default, this sample time is set to the minimum sample time of the solver according to the circuit-under-test. This value depends upon the complexity of the circuit, and ranges typically from 160 nanoseconds to 4 microseconds. A higher value can also be explicitly given, using the appropriate option in the Dual eHS block parameter panel.

The inputs and outputs of the eHS solver are sampled at the sample time indicated in the eHS parameter panel. Nevertheless, inputs coming from, and outputs received by the RT-LAB model will be sampled at the RT-LAB sample time, which is typically longer (see Figure 16 below).

Gated signals sent using the RT-EVENTS signal type “RTE Boolean” have a time resolution higher than the RT-LAB model sample time, and are thus sampled at the eHS sample time.⁶

Because of inherent communication procedures between the FPGA-based hardware and RT-LAB, a latency of two RT-LAB time steps is observed between the time when commands are sent to the eHS and when its response in the circuit can be read again in RT-LAB, as shown in 0below:

Interconnecting Multiple eHS Solvers

As previously explained, gated signals have a time resolution higher than the RT-LAB simulation step size. These signals are typically pulse-width modulated signals (PWM), and are generated by the FPGA firmware with a time resolution in the order of 10 nanoseconds. Hence, these signals can be sampled at the eHS computation rate.

On the other hand, input signals generated by RT-LAB will, by default, be sampled with a sampling period equal to the RT-LAB simulation step size, which is in the order of 10-50 microseconds. A better resolution can be achieved either by generating the signals directly on the FPGA, by taking inputs from the external world via an analog input interface, or by interconnecting multiple eHS solvers.

By default, eHS sources are accessed through the eHS block and are sent from the CPU of the simulator.

As illustrated in Figure 18 below, the source control signals of either eHS can come from RT-LAB, from the output of the other eHS solver, or from any other FPGA-based solver. The selection is made for each individual signal in the “Input Settings” tab by routing the control of a source by another eHS output.

Using the Scenario Feature

What Is a Scenario?

A scenario is a version of the netlist that has its own parameter set (i.e. Capacitors/Inductances/Resistances).

The scenarios feature makes it possible to have multiple versions of the netlist stored in the FPGA solver core. Thus, during runtime, the user is able to switch from one scenario to another in order to modify the model behavior. For example, this could allow the user to apply short or open circuit faults.

The scenarios are managed inside an XLS file. For each scenario, a line is declared, and for each component involved in a scenario, a column is added in the XLS file. For a given scenario, it is possible to modify as many components values as required by the scenario.

Writing the XLS Scenario File

Getting Started

The easiest way to write the first XLS file is to generate a template by selecting the Create an XLS template for the current netlist option from the Scenario Management tab. Users can also write the XLS file themselves. The first line, from cell B1, is reserved for RLC components declaration. The first column, from cell A2, is reserved for the scenarios declaration.

Filling the Component Line

The first line of the table, starting at cell B1, is reserved for the component declarations. The component name is the netlist name (from the top-level of the netlist, e.g. subsystem/componentname). If the component is inside a branch, its name will be the branch name with the suffix ".R", ".L" or ".C", depending on the type of the targeted component.

Filling the Scenario Column

The first column of the table, from cell A2, is the scenario declaration. Scenario labels must respect the following naming convention: Scenario followed by the scenario number (e.g. the correct scenario 21 will be labeled Scenario21).

Default Scenario Line

The Default label is reserved to display the default values of each component. However, these are not applied to the netlist as default values but are only there for information. Instead, the netlist file components values are applied by default.

Removing Lines/Columns

Removing lines (scenarios) and columns (components) from the table is allowed. As a result, the removed scenarios and components will be kept at default values.

Filling the Table

For each scenario, the component parameters to be modified need to be defined. These scenario component values are to be entered in the table. Leaving a cell empty will keep the component's value unchanged by the scenario, thus maintaining its default value.

Number of Modifications Allowed by Scenario

For each scenario, all declared components’ values can be modified. There is no limitation on the number of components that can be edited by each scenario.

Non-Existing Component

If a component is declared in the XLS file, but does not exist inside the netlist (e.g. if there is the wrong label or a component was removed), this column will be ignored and this will not have any effect on the scenario generation.

Non-Existing Scenario Declaration

If a scenario is impossible (wrong label or scenario number greater than the maximum number of feasible scenarios), an error will be thrown.

Verifying that Scenarios Have Been Properly Generated

While generating the eHS configuration, a log is generated in the MATLAB command prompt to advise the user of the changes made to the netlist depending on the scenario number.

The Loss Compensation Algorithm (LCA) Feature (eHS Gen3 Only)

What is the LCA?

The Loss Compensation Algorithm (LCA) feature removes the power losses that might occur when an IGBT/Diode switch is used (as a result of the Pejovic method). This technique works only for specific converter topologies.

Currently, only eHS Gen3 supports this feature.

Recognizing the Gen3 Block

As shown in Figure 21 above, the Gen2 and Gen3 eHS blocks are very similar. The main difference is the support for the LCA feature that is only accessible with the eHS Gen3 block.

Supported Topologies

The following two topologies support the LCA feature:

• The two-level arm converter

• The three-level NPC arm converter

How to Use the LCA Feature (SPS Workflow)

Using LCA with a Two-Level Arm Converter

To use the LCA in the SPS environment the two-level arm converter should be replaced by the universal bridge component in the eHS circuit model.

Once the circuit model has been updated with the universal bridge component, the user should rebuild the CPU-model in RT-LAB. During the eHS circuit parsing process, the universal bridge will be detected as an LCA element and the loss-compensation algorithm will be used instead of the classic switching logic.

Using the LCA Feature on a Three-Level NPC Arm Converter

To use the LCA feature in the SPS environment, the three-level NPC arm converter should be replaced by the Three-Level Bridge component in the eHS circuit model.

Once the circuit model is updated with the Three-Level Bridge component, the user can rebuild the CPU-model in RT-LAB. During the eHS circuit parsing process, the Three-Level Bridge component will be detected as an LCA element and the loss-compensation algorithm will be used instead of the classic switching logic.

Example Models and Templates

All eFPGAsim example models and template can be found in MATLAB>>Help>>eFPGAsim Blockset Demos or in the installation folder at the following path: <eFPGAsim Installation Directory> /Examples, where the eFPGAsim installation directory is located at C:/OPAL-RT/eFPGAsim by default.

Each example contains its own Help documentation located in the CPU model. Please refer to these models for getting started with the eHS.