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This model represents a decoupling point on a line by modeling the line parameters and de-coupling latency between CPU and FPGA. The line inductance or capacitance also need to be defined.
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Parameters
Symbol | Name | Description | Unit | Type |
|---|---|---|---|---|
Type | Half Line conductance type | Conductance type of the half line. Either inductive or capacitive. | N/A | Input |
Inductance / Capacitance | Half Line conductance value | Conductance value of the half line. Either inductive or capacitive based on selected Type | L / F | Input |
De-coupling latency | CPU / FPGA de-coupling latency | Latency in seconds between FPGA and CPU. When set to “Auto”, eHS will try to determine a valid value based on circuit parameters, The value can be manually edited if the automatic estimate doesn’t match expected results. | s | Input |
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