Digital Inputs Configuration Page
This page is populated with a list of the Digital Input channels available for the selected Hardware Configuration.
The following configuration options are available at edit-time:
Digital Input Settings | |||
Enable PWM Measurement Channels | Enables the PWM Measurement feature for every Digital Input channel. | ||
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When this option is enabled, an Advanced subsection is created under the Digital Inputs section and populated with ConnX.DIXX Duty Cycle and ConnX.DIXX Frequency channels as described in the table below. |
Digital Inputs Section Channels
This section includes the following custom device channels:
Channel Name | Type | Units | Default Value | Description |
|---|---|---|---|---|
ConnX.DIXX Duty Cycle | Output | Percent | 0% | Duty Cycle of the digital signal acquired on channel |
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ConnX.DIO<XX>. |
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Accuracy information can be found under PWM Measurement Accuracy. When Enable PWM Measurement Channels is enabled, the Digital Inputs >> Advanced >> Duty Cycle section is populated with one |
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ConnX.DIOXX Frequency channel for each Digital Input channel. | ||||
ConnX.DIXX Frequency | Output | Hertz | 0Hz | Frequency of the digital signal acquired on channel |
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ConnX.DIO<XX>. Accuracy information can be found under PWM Measurement Accuracy. When Enable PWM Measurement Channels is enabled, the Digital Inputs >> Advanced >> Frequency section is populated with one |
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ConnX.DIOXX Frequency channel for each Digital Input channel. | ||||
ConnX.DIXX | Output | 0 | Digital data read by the FPGA on channel |
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ConnX.DIO<XX>. The Digital Inputs section is populated with one |
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ConnX.DIOXX channel for each Digital Input channel available in the selected Hardware Configuration. |
Digital Input data can be mapped to other simulation components by navigating to their respective configuration pages listed below. Mapping options may vary between Hardware Configurations.
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| Anchor | ||||
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The accuracy of the PWM Measurement feature is dependent upon the frequency and duty cycle of the measured signal.
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The tables below provide benchmark information describing the maximum expected measurement error across a range of PWM frequencies.
Table 1: Error in Frequency Measurement
These data points have been validated for Duty Cycles between 0.1 and 0.9.
Table 2: Error in Duty Cycle Measurement
Duty cycle error has been measured at three Duty Cycles: 0.1, 0.5, and 0.9.
Frequency Range | Percent Error in Duty Cycle Measurement Duty Cycle: 0.1 | Percent Error in Duty Cycle Measurement Duty Cycle: 0.5 | Percent Error in Duty Cycle Measurement Duty Cycle: 0.9 |
|---|---|---|---|
1Hz - 10Hz | < 0.0005% | Negligible | Negligible |
10Hz - 100Hz | < 0.005% | < 0.001% | < 0.001% |
100Hz - 1kHz | < 0.05% | < 0.01% | < 0.01% |
1kHz - 10kHz | < 0.1% | < 0.05% | < 0.05% |
10kHz - 100kHz | < 1% | < 0.1% | < 0.1% |
100kHz - 500kHz | < 10% | < 2% | < 1% |
Table 3: Minimum Detected Frequency
If a signal with a frequency below the Minimum Detected Frequency is applied, the corresponding VeriStand Channels will output NaN (Not a Number) after the Settling Time has elapsed.
Hardware Configuration | Minimum Detected Frequency | Settling Time |
|---|---|---|
0.5 Hz | 2 s | |
0.5 Hz | 2 s | |
0.25 Hz | 4 s | |
0.25 Hz | 4 s |