Power Electronics Add-On Custom Device

Power Electronics Add-On Configuration Page

In the System Explorer window configuration tree, expand Targets >> Controller >> Custom Devices and select Power Electronics Add-On to display this page. If this is a new VeriStand project, see the instructions in How to Add the Power Electronics Add-On to the System Definition.

This page includes the following components, configurable at edit-time only:

Ribbon Buttons
Launch HCM	Launches the Hardware Configuration Manager. The Hardware Configuration Manager (HCM) is a tool used to create, edit, and remove Hardware Configurations
Right-Click Menu
Enable/Disable	Specifies if the Power Electronics Add-On real-time engine is Enabled or Disabled. Disabling the Power Electronics Add-On using the right-click menu does not impact the system definition. A user can continue to view and modify the system definition and the custom device files will still be deployed to the real-time target. However, the Power Electronics Add-On engine will not execute on the target.

Power Electronics Add-On Main Page
Version	Specifies the version of the Power Electronics Add-On.
Configuration	Selected Hardware Configuration for the project. The configuration defines the types of FPGA boards to be targeted and the features available in their firmwares.
Configuration Description	Description of the features included in the selected hardware configuration. For more detailed information about a configuration, navigate to its Help page under Default Hardware Configurations.
Target	Name of the FPGA target onto which the corresponding bitfile will be deployed. This must match the name of the FPGA target as displayed in the NI Measurement and Automation Explorer.
Bitfile	File name of the bitfile to be deployed to the FPGA target.
Target Credentials
Username	Specify the username for the NI Real Time Target. The default target username is admin. Target credentials can be modified in the NI Measurement and Automation Explorer.
Password	Specify the password for the NI Real Time Target. The default target password is an empty string. Target credentials can be modified in the NI Measurement and Automation Explorer.
Advanced Performance
Enable Telemetry Channels	Allows telemetry parameters to be exposed as VeriStand Channels. See Telemetry Channels below for more details.
Processor Assignments	Launches the Processor Assignments dialog window.

Power Electronics Add-On Section Channels

This section includes the following custom device channels:

Advanced Channels

Element Name

Type

Units

Description

Reset Models

Input

This channel resets all models in the custom device, such as eHS cores and machine model cores.

Set this channel to one of the following values:

0 - All models in the custom device will execute as configured
1 - All models in the custom device will be set into a Reset mode until the Reset Models channel is set back to 0.

Models in Reset mode do not react to inputs, and their outputs should not be considered as valid. Please refer to the Reset Model Behavior section for more information.

Telemetry Channels

Section

Contains the Telemetry Channels. This section is made available when Enable Telemetry Channels is enabled.

Telemetry Channels

When Enable Telemetry Channels is enabled, the Telemetry Channels section is added to the configuration tree. The channels are grouped according to the process to which they belong. FPGA Communication Processes 1, 2, and the Low Latency FPGA Communication Processes are responsible for CPU-FPGA communication (read/write), while the Waveform Acquisition Process is responsible for the acquisition of stream data from waveforms.

	Channel Name	Type	Units	Description
FPGA Communication Process 1
	Actual Loop Rate	Output	Hz	The execution rate of the FPGA Communication Process.
	Iteration	Output		The iteration count of the FPGA Communication Process.
	Write Time	Output	us	Time taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.
	Read Time	Output	us	Time taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.
	Iteration Duration	Output	us	Time taken to execute the last entire iteration of the process.
	Finished Late Count	Output		Number of iterations that have exceeded the specified Loop Rate for this process.
FPGA Communication Process 2
	Channel Name	Type	Units	Description
	Actual Loop Rate	Output	Hz	The execution rate of the FPGA Communication Process.
	Iteration	Output		The iteration count of the FPGA Communication Process.
	Read Time	Output	us	Time taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.
	Write Time	Output	us	Time taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.
	Iteration Duration	Output	us	Time taken to execute the last entire iteration of the process.
	Finished Late Count	Output		Number of iterations that have exceeded the specified Loop Rate for this process.
Low Latency FPGA Communication Process (One per FPGA Target with Low Latency Support)
	Channel Name	Type	Units	Description
	Actual Loop Rate	Output	Hz	The execution rate of the Low Latency FPGA Communication Process.
	Iteration	Output		The iteration count of the Low Latency FPGA Communication Process.
	Write Time	Output	us	Time taken by the Low Latency FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.
	Read Time	Output	us	Time taken by the Low Latency FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.
	Iteration Duration	Output	us	Time taken to execute the last entire iteration of the process.
	Finished Late Count	Output		This data is not available for Low Latency FPGA Processes. The channel value is always -1.
	Late Samples	Output		Number of samples that have been sent late from the Low Latency Process to the Low Latency Engine on the FPGA. This indicates that the CPU has fallen behind.
	FPGA System Loop Time	Output	Ticks	Measured execution rate of the Low Latency Engine on the FPGA.
	CPU Load Time Value	Output	Ticks	Time measured from the start of the FPGA-to-CPU write data transfer to the completion of the CPU-to-FPGA read data transfer.
	CPU Load Time Maximum	Output	Ticks	Maximum CPU Load Time Value.
	Transfer Sequence Number	Output		FPGA-to-CPU Transfer Sequence Number. This value is incremented by the FPGA engine after the FPGA-to-CPU data is transferred to the CPU.
	FPGA Communication State	Output		Last reported state of the Low Latency Engine on the FPGA.
Waveform Acquisition Process
	Channel Name	Type	Units	Description
	Actual Loop Rate	Output	Hz	The execution rate of the Waveform Acquisition Process.
	Iteration	Output		The iteration count of the Waveform Acquisition Process.

Reset Model Behavior

When the Reset Models channel is asserted, all models in the custom device will be reset and placed into a paused state until the channel is deserted. When the models are in the reset state, certain outputs of the model will not be set to back to 0, Instead, they may retain their latest valid value before the reset channel was asserted. This behavior is a known issue in the product and may change in the future.

How to Add the Power Electronics Add-On to the System Definition

Power Electronics Add-On Configuration Page

Power Electronics Add-On Section Channels

Telemetry Channels

Reset Model Behavior

Related Links