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Number of portsAllows the user to specify the number of data ports available for this block. When the number of ports is changed, other parameters are updated accordingly.

Transfer mode

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Parameter_Transfer_mode
Parameter_Transfer_mode

Allows a user to choose whether to synchronize incoming data, where only one data sample can be transferred per calculation step, or to admit asynchronous mode, where up to 254 samples can be transferred per calculation step.

For example, a value of 010000000000101 in this field sets ports 1 and 3 and 15 (MSB to LSB port representation) to asynchronous mode.

Provide Start Of Frame

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Parameter_Provide_SoF
Parameter_Provide_SoF

When active (value=1), an output port SofIN is added to the block right below the corresponding DataIN port number.

For Example, a value of 010000000000101 in this field adds and sets SofIN ports 1 and 3 and 15 (MSB to LSB port representation) to output the Start of Frame pulse.


Enable/Disable Data Protection
Allows the user to activate/deactivate the protection feature. In protective mode, the Valid Data is allowed to pass only on Application Execute or Pause State. It should be noted that on Pause State, the data validation is allowed to pass if there was an Execute on the previous state. In addition, the protective mode allows the user to set the default value of the output.
This functionality will be removed with RT-XSG 3.3.3
Align Start Of Frame
When disabled, the Start of Frame pulse occurs right before the first valid data of the incoming data frame at each calculation step. When enabled, it occurs in synchronization.

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DataINX where X=[1 to 64]

Each of those ports is a signal with a UFix33_0 format. For these signals, the first 32 bits represent the data and bit 33 (most significant bit) is the valid bit, indicating when the information is updated.

  • In synchronous mode (default) the valid bit is in sync with the ModelSync or model calculation step (active high for one FPGA clock duration);
  • In asynchronous or in burst mode, the valid bit is active on arrival of the data.

SofINX where X=[1 to 64]

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Output_SoFIN
Output_SoFIN

Those ports are shown on the block when the parameter Provide Start Of Frame enables it. The corresponding port provides a pulse signal of one FPGA clock duration.

The provided signal allows the user to easily unpack the data when multiple data are being received per calculation step through the same port, which is the case when Transfer mode is set to asynchronous for the specified port.

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