Block

Mask

Description

This block represents the input link of the FPGA through the PCIe bus. Data may be coming from the PC target or from another FPGA in a multiple chip design. 64 ports are provided for data samples and control signals.

One of the functions of this block is to perform data conversion from uint32 to the System Generator UFix33_0 data format. It is up to the user to extract the desired data out of the 32 least significant bits and to reinterpret these bits to the desired format (signed or unsigned with or without binary point).

This block is linked, depending on the RT-LAB flow, to

the inputs of the OpCtrl Reconfigurable IO block found in the RT-LAB CPU model: port #1 of the OpCtrlReconfigurableIO corresponds to DataIN1, port #2 to DataIN2, etc.
the connection points established through OPALBOARDS.

Parameters

Number of ports	Allows the user to specify the number of data ports available for this block. When the number of ports is changed, other parameters are updated accordingly.
Transfer mode	Allows a user to choose whether to synchronize incoming data, where only one data sample can be transferred per calculation step, or to admit asynchronous mode, where up to 254 samples can be transferred per calculation step. For example, a value of 010000000000101 in this field sets ports 1 and 3 and 15 (MSB to LSB port representation) to asynchronous mode.
Provide Start Of Frame	When active (value=1), an output port 48300464 is added to the block right below the corresponding DataIN port number. For Example, a value of 010000000000101 in this field adds and sets SofIN ports 1 and 3 and 15 (MSB to LSB port representation) to output the Start of Frame pulse.
Enable/Disable Data Protection	Allows the user to activate/deactivate the protection feature. In protective mode, the Valid Data is allowed to pass only on Application Execute or Pause State. It should be noted that on Pause State, the data validation is allowed to pass if there was an Execute on the previous state. In addition, the protective mode allows the user to set the default value of the output. This functionality will be removed with RT-XSG 3.3.3
Align Start Of Frame	When disabled, the 48300464 pulse occurs right before the first valid data of the incoming data frame at each calculation step. When enabled, it occurs in synchronization.

Input

Data_IN	This is a vector of 64 uint32 type signals. Each of these signals represents an input port on the OpCtrlReconfigurableIO block of the RT-LAB CPU model or is related to a connection point under OPALBOARDS.

Outputs

DataINX where X=[1 to 64]

Each of those ports is a signal with a UFix33_0 format. For these signals, the first 32 bits represent the data and bit 33 (most significant bit) is the valid bit, indicating when the information is updated.

In synchronous mode (default) the valid bit is in sync with the ModelSync or model calculation step (active high for one FPGA clock duration);
In asynchronous or in burst mode, the valid bit is active on arrival of the data.

SofINX where X=[1 to 64]

Those ports are shown on the block when the parameter 48300464 enables it. The corresponding port provides a pulse signal of one FPGA clock duration.

The provided signal allows the user to easily unpack the data when multiple data are being received per calculation step through the same port, which is the case when 48300464 is set to asynchronous for the specified port.

Characteristics and Limitations

This block has no special characteristics or limitations.

DataIn