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Description
The FPGA Synthesis Manager is a convenient utility to manage model translation into FPGA interpretable VHDL code and to integrates this model into the framework of the OPAL-RT communication and I/O interfaces. It enables the user to generate a programming file for the reconfigurable chip of various boards. It also enables the automatic Programming of the board using a JTAG connection.
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Note: For a system using eHS, you may apply a 200MHz clock. |
- Oversampling Clock Frequency: This parameter specifies the clock frequency used as the based clock for the Digital input Oversampling feature. The Digital inputs will be sampled 4 times per Oversampling clock cycle (so effectively at 4 times the oversampling frequency). By default, 400Mhz is used for the eHS Gen5 block on Kintex-7 and Virtex-7 FPGA, 500Mhz is used on Versal FPGA.
- A clock will be generated at the frequency specified by this option, and could be used to clock Asynchronous blackbox design. To use the generated clock, use a block FROM with the global tag "OversamplingClock_0".
- Implementation Strategy: This parameter gives to the user new strategies in addition to the default one. It is hardly recommended to keep the default one unless the timing closure is not reached with it. In other words, if the user encounters some timing errors, he can proceed to a new iteration of generating a bitstream by using another implementation strategy that is more suitable to its design. Using directly other strategy than the default one right at the first iteration of generating a bitstream without knowing that its timing closure can be reached, is not recommended.
- This parameter presents the list of the available implementation strategies to be use during the bitstream generation process. Refer to Xilinx's UG904 documentation and UG835 for information on the syntax and effect of each strategies to help choosing one of the available strategies.
- Selecting "User defined" and going through the configuration will end-up saving the established strategy under a folder within the RT-XSG's installation path. Primary folder will be named "AppData_RTXSG" and the secondary folder will have the name given to the strategy. The strategy can then be shared and reused and could be deterministic (depends on Xilinx tool revision).
- This parameter presents the list of the available implementation strategies to be use during the bitstream generation process. Refer to Xilinx's UG904 documentation and UG835 for information on the syntax and effect of each strategies to help choosing one of the available strategies.
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