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The block can have up to 64 ports of 33 bits in the Xilinx UFix format (not applicable for OP4200 unless implemented in a future release). Data coming from the DataIN block is updated at the rate of the CPU model simulation time step. The receive mode can be either synchronous or asynchronous.
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One I/O Block must be instantiated in the model for each I/O module of the chassis. The mask parameters are as follows:
Type | Type of signal to be interfaced (either analog or digital) |
|---|---|
Direction | The direction of the signal to be interfaced (either input or output) |
Interface | This drop-down menu lists all available interfaces available according to the selected Type and Direction parameters and the hardware platform selected in the Hardware Config block. The user chooses the appropriate interface to manage the specific signal. |
Characteristics | This is not editable. It shows the interface board characteristics for easy identification of the board that corresponds to the selected interface location |
Multiplex input/output signals | This checkbox can be used to concatenate multiple inputs or output signals on the same Simulink R net. This may help the user to build cleaner schematics |
Number of channels | This is used to select the number of channels to appear on the block icon. This option is not available when the Multiplex input/output signal option is selected. In this case, the channel number is set to the maximal value allowed by the selected interface board |
Show external signal port(s) | This is used to add input or output ports that represent the external world, from the active control card point of view. These ports can be used to connect the signals to a model of the external device connected to the signal conditioning modules. This feature can be very useful for offline simulation of the FPGA model |
Once the signal type (analog or digital) and direction (input or output) are selected, the Interface drop-down list allows selecting one of the I/O module installed in chassis, as well as the Default Output Values.
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| Warning |
|---|
By disabling the strict hardware mismatch in the simulation software, the designer assumes entire responsibility of securing its hardware. |
DeviceID (in the bitstream) | Compatible with (in the hardware) |
|---|---|
OP5340 | OP5340; OP5340-2 |
OP5340-2 | OP5340; OP5340-2 |
OP5330-1 | OP5330-1; OP5330-3 |
OP5330-3 | OP5330-1; OP5330-3 |
OP5351 | OP5351; OP5353; OP5357; OP5358-3; OP5358-5 |
OP5353 | OP5351; OP5353; OP5357; OP5358-3; OP5358-5 |
OP5357 | OP5351; OP5353; OP5357; OP5358-3; OP5358-5 |
OP5358-3 | OP5351; OP5353; OP5357; OP5358-3; OP5358-5 |
OP5358-5 | OP5351; OP5353; OP5357; OP5358-3; OP5358-5 |
OP5352 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5354 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5355 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5356-3 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5356-5 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5359 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5360-1 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2, OP5360-3 |
OP5360-2 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5360-3 | OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 |
OP5367-1 | OP5367-1 |
OP5367-3 | OP5367-3 |
OP5367-5 | OP5367-5; OP5367-6 |
OP5367-6 | OP5367-6; OP5367-5 |
OP5369 | OP5351; OP5353; OP5360-1; OP5360-2; OP5360-3 |
OP5969-2 | OP5969-2; OP5969-1 |
OP5969-1 | OP5969-2; OP5969-1 |
OP7820 | OP7820; OP7822 |
OP7822 | OP7820; OP7822 |
OP7817-2 | OP7817-2; OP7821 |
OP7821 | OP7817-2; OP7821 |
Analog Output Interface
One Analog Output block is used to access all 16 channels of one Analog Output mezzanine installed on the simulator.
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