FPGA Model Overview

When designing a real-time simulation for an OPAL-RT platform, two Simulink models must be created.

• The first one, hereafter called the FPGA model, contains the RT-XSG blocks required to build the configuration file to be downloaded in the FPGA of the real-time platform. The sections below describe the blocks used to build this model.

• The second model, the CPU model, will run on the CPU of the real-time platform and is controlled by the simulation software (RT-LAB or HYPERSIM). This model contains interface blocks (OpCtrl and IO functionality blocks, or OpInput/OpOutput blocks) that allow exchanging information between the CPU model and the FPGA board, through the PCIe bus. These blocks can be interpreted as a bridge between software and hardware.

Example CPU models are provided under RT-LAB software and FPGA models are provided under folder <RTXSG_ROOTFolder>\Examples and can be used as a start point for building your specific FPGA design and corresponding RT-LAB model.  

Inside the FPGA model, besides the logic to be implemented on the FPGA, certain blocks are required to establish communication with the CPU Model and also to interact with the IO cards.

The following figure shows the OP4510 I/O example model, which can be found at C:\OPAL-RT\RTXSG\v3.x.x.x\Examples\OP4510\AIO_DIO_TSDIO_PWMIO_QEIO.

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CPU-FPGA Communication Blocks

DataIN and DataOUT Blocks

The RT-XSG DataIN and DataOUT library blocks control data transfer to and from the CPU.

The DataIN block is used to receive data coming from the CPU model and pass them to the FPGA model at runtime.

The block can have up to 64 ports of 33 bits in the Xilinx UFix format. Data coming from the DataIN block is updated at the rate of the CPU model simulation time step. The receive mode can be either synchronous or asynchronous.

The DataIN block contains one input (Data_IN) that can be used for offline simulation, in synchronous mode. Each element of the vector connected at this input is provided on its associated DataINx output port.

During the generation process (and in the final bitstream file), this Data_IN input is automatically disabled and the blocks connected to it are discarded. The input of the DataIN block then becomes the values sent from the CPU model through the corresponding interface blocks.

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The synchronous mode is associated with the default mode of the DataIn Send block in the CPU model (one data per port per time-step) (that block is for usage with SFunction Driver, see RT-LAB documentation for more information and usage of OPALBOARD instead), there is not time multiplexing on the CPU side. This mode is shown in the figure above for three DataIN ports.

The asynchronous mode is used when there is time multiplexing on the CPU side. It returns up to 250 words to the FPGA model during each CPU time step. The exact time of arrival in the FPGA model is unknown.

The Start of Frame option, allows the user to easily unpack the data when multiple data is being received per calculation step through the same port (asynchronous mode). This signal is a pulse, of one FPGA period clock duration, and it is received right before the first valid data of the incoming data frame at each calculation step.

For Example, a value of 010000000000101 in this field sets input ports 1 and 3 and 15 (MSB to LSB port representation) to output the Start of Frame pulse. For this, new ports labeled SoftIN3, SoftIN5, and SoftIN15 will appear right below the corresponding DataIN port number.

The DataOUT block is used to send data from the FPGA model to the CPU model at runtime. The block can have up to 64 ports of 33 bits (see Augmented Dword 33 Bit Data Vectors) in the Xilinx UFix format.

These can be synchronized and the send mode can either be register or FIFO.

The sample period is usually 10ns on the input ports of the block but data samples are sent to the CPU model at the CPU model rate.

The block has the capability to show the values to be sent to the FPGA model through its Data_Out output port during an offline simulation. During generation (and in the final bitstream file), this output port is not used.

The register mode is used when time multiplexing is not needed. It returns one word to the CPU model at every CPU time step. Only the last data computed on the FPGA is sent to the CPU model.

The FIFO mode is used when time multiplexing is needed. The « buffer » on the FPGA can store up to 250 words. To decide if a sample will be stored or not, the block looks for the MSB (bit 32) connected to that DataOut port.

The MSB is a valid bit. If the valid bit is 1, the sample is stored. If the valid bit is 0, the sample is discarded.

Considering those 3 FPGA steps that occurred in the order displayed, we will receive on the CPU model the results shown below.

LoadIN and LoadOUT Blocks

The LoadIN block is used to receive data coming from the CPU model and pass them to the FPGA model at a specific time.

The block can have up to 32 ports of 33 bits in the Xilinx UFix format (see Augmented Dword 33 Bit Data Vectors).

Data coming from one of the ports of LoadIN is updated only when its enable signal is received.

The receive mode can be either synchronous or asynchronous. It contains one input (Cfg_IN) that can be used for offline simulation.

The LoadOUT block is used to send data from the FPGA model to the CPU model at a specific time. The block can have up to 32 ports of 33 bits in the Xilinx UFix format. These can be synchronized and the send mode can either be register or FIFO. Data is sent out to the CPU only when the enable signal for the related port is received.

I/O Management

I/O Block

One I/O Block must be instantiated in the model for each I/O module of the chassis. The mask parameters are as follows:

Once the signal type (analog or digital) and direction (input or output) are selected, the Interface drop-down list allows selecting one of the I/O module installed in chassis, as well as the Default Output Values.

The number of input and output ports of the I/O Block depend upon the selected interface board.

Implementation of the external connections is also available to enable offline simulation of the complete system, including external hardware setup.

Hardware Compatibilities of Interface cards

The I/O modules supported on the OPAL-RT platforms can be grouped in families sharing the same global behavior, and a bitstream file generated for a given hardware configuration can be used on a system on which compatible I/O modules are installed.

The table below states these compatibility lists.

For example, a bitstream generated from an RT-XSG model in which the OP5330-1 was selected for a given section on the carrier, can be used on a chassis having an OP5330-3 installed in that section instead.

Note however that the simulation software (RT-LAB or HYPERSIM) allows enforcing a true match of the I/O module selected when preparing the model and the actual I/O modules detected on the carrier.

Analog Output Interface

One Analog Output block is used to access all 16 channels of one Analog Output mezzanine installed on the simulator.

Channels can be accessed individually or by groups of two if the option Multiplex is selected.

When channels are addressed individually, each input of the block represents one channel and must be driven by a Fix16_11 bit word. The MSB (bit 15) is the sign. Four bits (bits 14 to 11) represent the integer value while the remaining 11 bits (bits 10 to 0) represent the fractional part. This logic implies that the Analog Output range is within [+15.999, -16] volts. This is compatible with the DAC chip range and resolution used on OPAL-RT TECHNOLOGIES’ Analog Output mezzanine.

When signals are multiplexed (addressed by groups of two), each input of the block represents two channels and must be driven by a UFix33_0 bit word. The MSB (bit 32) is the valid bit. Bits 31 to 16 represent channel x+1 while bits 15 to 0 represent channel x. The valid bit must be set to 1 for the outputs to be active. Each channel must have a format equivalent to the Fix16_11 numeric format.

The update rate of the outputs can be selected by the user (down to 1us) through the Convert input of the block. To do so, the user must provide a pulse with the required period (for example 1us). The ModelSync signal can be used also. As of now, only one update rate can be selected for all 16 channels.

Analog Input Interface

One Analog Input block is used to access all 16 channels of one Analog Input mezzanine installed on the simulator.

Channels can be accessed individually or by groups of two (Multiplex option selected). The acquisition rate of the inputs can be selected by the user (down to 2.5us) through the Convert input of the block. To do so, the user must provide a pulse with the required frequency (for example 2.5us). As of this writing, only one acquisition rate can be selected for all 16 Analog Input channels.

When channels are addressed individually, each output of the block represents one channel and is a Fix16_10 bit word. The MSB (bit 15) is the sign. Four bits (bits 14 to 10) represent the integer value while the remaining 10 bits (bits 9 to 0) represent the fractional part. This logic implies a range of [+31.999, -32] volts.

The ADC mezzanine by default can do [+20, -20].

When the Multiplex option is selected (groups of two), each output of the block represents two channels and is a UFix33_0 bit word. The MSB (bit 32) is a valid bit. Bits 31 to 16 represent channel x+1 while bits 15 to 0 represent channel x. Each channel is represented using Fix16_10.

Digital Output Interface

One Digital Output block is used to access all 32 channels of one Digital Output mezzanine installed on the simulator. Channels can be accessed individually or merged in a single 32-bit word.

The update rate is limited by the hardware conditioning only. At some point, the rising time of the digital output becomes too important compared to the period of the digital signal/PWM. At this point, logic level detection does not occur fast enough for the duty cycle to be properly represented.

When channels are addressed individually, each input of the block represents one channel and must be driven by a 1-bit word. When grouped in a 32-bit word, bit 0 (LSB) will drive channel 0 while bit 31 (MSB) will drive channel 31. A low voltage level is sent as 0 while a high voltage level is sent as 1. The voltage level itself is set by the user at the hardware level (for example 0 to 5V, 0 to 12V, etc.).

Digital In Interface

One Digital Input block is used to access all 32 channels of one Digital Input mezzanine installed on the simulator. Channels can be accessed individually or retrieved in a single 32-bit word. The update rate is limited by the hardware conditioning only.

When no multiplexing, each output of the block represents one channel, coded on 1 bit. When grouped, bit 0 (LSB) represents channel 0 while bit 31 (MSB) represents channel 31. A low voltage level is returned as 0 while a high voltage level is returned as 1.

Simulation State Blocks

The Simulation State block returns the various states of the CPU model to the FPGA model. The CPU model states are Stopped, Pause, Execute, Reset and Load. The Simulation State returns one if the state is true/active and returns zero if the state is false/inactive. Each output has a size of 1 bit.

ModelSync Tag

Synchronization pulse train whose period is equal to the specific CPU application time step is available as a signal named ModelSync (available by using a Simulink From block). This rate is adjusted to the actual CPU model step size at the start of the CPU model execution.

This rate typically ranges from tens to hundreds of microseconds, which is much larger than the FPGA clock period (usually 10ns).

For I/O mapping FPGA generation, it can be used to set the update rates of the I/O blocks or the DataOut block synchronization for example. The tag can also be used for any other purposes at any place in the FPGA model.

For the user’s reference, this ModelSync From tag is linked to the ModelSync GoTo tag, found (hidden) under the RT-XSG Version block.