Introduction

This document describes how to create a FPGA-based Custom Model that will connect to other ioconf compatible features and be included in automatic firmware description file generation. Using the template Custom Model block from eFPGASIM’s XSG library, define input and output signals to easily connect to eHS and the CPU using Schematic Editor.

To get familiar with the Custom Model block, see the related help pages for the Custom Model XSG and CPU blocks:

https://opal-rt.atlassian.net/wiki/spaces/PFPETFPET/pages/982417894

https://opal-rt.atlassian.net/wiki/spaces/PFPETFPET/pages/982451131

Requirements

• eFPGASIM 2.19 and higher

• RT-XSG 3.7.0 and higher

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1. Drag and drop the Custom Model block from the library into your model.

   

2. For eHS connectivity, connect your custom model to an eHS FLWS input, the eHS low latency output and a new Load In.

   

3. For CPU connectivity, connect your custom model to a new Data In and Data Out.

   

4. Now that the custom model is imported, open the mask. Inside the mask are editable text fields to specify the names of the signals. Leave them as is or edit them. By default, there are three inputs and outputs connected to eHS and to the CPU (CPU connection capabilities is ONLY available in S_FUNCTION workflow!). Once the proper signals are set, click the “Open Custom Model Design” button to start editing. If you need any extra inputs or outputs coming from or going to other blocks other blocks then eHS, use the Input/Output Bus checkboxes. These checkboxes add an input and output port to the custom model that can be used to connect with the rest of the firmware model.

   

5. Add your custom FPGA-based logic under the block and connect your inputs and outputs. Notice the path, under the “custom” subsystem is exclusively where modifications to the model should be made. This subsystem is opened via the “Open Custom Model Design” button. The signal connected to eHS are expected to be Extended Floats (XFLOAT_8_34). The signals connected to the CPU are expected to be Unsigned Fixed 32 bits (UFIX_32_0).

   

6. Once your design is complete, the model is ready for bitstream and ioconf generation. In this example, the signals coming from eHS are multiplied by 2, 3 and 4 and sent back to eHS. The signals coming from the CPU and added by 10, 20 and 30 and sent back to the CPU.

   

7. Create a RT-LAB project, add a eHS SE block and a Custom Model block. To use the Custom Model CPU block, make sure the .ioconf associated to the fimware binary file is in the project folder or Matlab path.

   

8. Using the generated ioconf file, the Custom Model should now be visible in the Schematic Editor’s external model inputs and outputs!

   

9. In the RT-LAB model, select the Custom Model to configure in the mask dropdown.

   

10. The source in the Schematic Editor model will be multiplied by 2, 3 and 4 and the signals send from the CPU will be added by 10, 20 and 30!

    

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