This chapter covers important topics related to the creation of an RT-XSG Simulink model. It is assumed that the user is already familiar with the System Generator for DSP toolbox.

System Generator for DSP Toolbox

System Generator for DSP is a toolbox provided by Xilinx that consists of two Simulink simulation libraries.

Using the blocks in these libraries and blocks from the RT-XSG library, a user can construct and simulate their own FPGA design, download it to the FPGA chip of the reconfigurable I/O card supported by OPAL-RT TECHNOLOGIES, and integrate it in a real-time simulation.

The System Generator for DSP toolbox also allows the user to create and simulate their own FPGA design without the need for traditional HDL languages, all in a MATLAB/Simulink environment.

The design can implement DSP algorithms like filters, CORDIC algorithms, PWM generators, waveform generators and much more, and can interface with the I/O cards supported by OPAL-RT TECHNOLOGIES.

Gateways

The System Generator for DSP toolbox is able to convert a model-based Simulink design into a Hardware Description Language (HDL) file.

A programmable device configuration file is then generated from this HDL description. Input and output ports of the model to be implemented in such devices are inserted in the Simulink model as Gateway In and Gateway Out blocks, from the Xilinx blockset.

In an RT-XSG model, the target board is selected by the user in the first designing steps. As the board layout is fixed, the user does not have control of the input and output port definition. The RT-XSG library block sets provide the user with all the necessary interface blocks. Although the Gateway In and Gateway Out blocks are not directly visible by the user on the top hierarchical level of the model, they are still present under the mask of each of these blocks.

The figure below presents interface blocks that encapsulate Gateway In/Out blocks and are used for all supported hardware. In general, interface blocks between the User model and the external world show a blue-yellow background pattern (b), while interface blocks between the user model and an RT-LAB CPU model have a blue turquoise background pattern (a).

Other interface blocks may be found in the library of each specific FPGA (available via the Simulink browser), to address specific hardware or support specific communication protocols.

Mandatory Blocks

Target Platform Selection

The target platform is selected from the OPAL-RT FPGA Synthesis Manager block, located in the RTXSG/ Tools Blockset.

The target platform is selected by the FPGA development board drop-down list. Many configuration settings are automatically set upon the selection of the target platform.

Configuration File Version Selection

The configuration file version is used to identify the function of any FPGA configuration. From RT-LAB, users can retrieve the configuration file version used to configure any RT-XSG-compatible programmable device. The configuration file version is the combination of the release identification number (Version) and the minor identification number (Minor ID). Generally, a single minor identification number is assigned to specifically intended behavior of the FPGA configuration, while the release identification number identifies subsequent versions of the same design.

The figure below shows the Version parameter fields, used to set those two identification numbers, available when clicking on Version Configuration. . . from the SynthesisManager block.

Hardware Configuration Setup

The Hardware Configuration panel is provided to help the user select the appropriate analog or digital, input or output signal interface of the targeted system. The user should specify in this block the exact configuration of the I/O modules of the system.

The user can also affect a Default Output Value to each channel of the output module.

The Hardware Configuration panel is shown below and is used to set the Active Control card, Chassis from factor and the I/O cards configuration. It is available when clicking on Hardware Configuration. . . from the SynthesisManager block.

• Active Control Card: Automatically updated.
• Chassis Form Factor: Automatically updated.
• Hardware Configuration: Select the carrier type and then the corresponding modules.

Once this block is configured, the user can place instances of the IO Block  (blue-yellow block show above) in the RT-XSG model to link the logic with the channels of the I/O interfaces. The IO Block provides the user with all the available signal interface board locations according to the requested signal type (analog or digital) and direction (input or output).

Default Output Value Behavior

A bitstream starts running and driving I/Os shortly after the simulator is powered on, as soon as the bitstream configuration is loaded from memory into the FPGA chip. At that time, the output lines are set in the state defined when designing the bitstream in RT-XSG and remain in that state until the user can control the state of the output lines from the real-time simulation.

To protect the system ad set default values on the I/O lines in the time interval between the power-up of the system and the launch of the simulation, a set of options was defined to manage the Default Output Values.

Keep in mind that this protection is controlled by the FPGA and is thus active only when the FPGA is programmed. It is not intended to control the I/O lines during power-up or in case of power shutdown which can result in uncontrolled voltage levels for a short period of time. For very sensitive hardware, make sure to implement external hardware protection to protect against these situations.

Accessed by clicking the small gear icon which appears next to the selection list when an I/O module is selected, the user can choose to affect a specific behavior of output value for each channel which is indicated by the line number of the internal table. A menu to configure the channels related to an IO Block is identified in the name of the window, below.

The applied specific behaviors are independent. They respectively take place when the simulation model’s state is Pause or Reset.

For each of these model’s state, the Default Output Value can behave as:

• Set the output to Assigned value: when the associated model’s state takes place, the value in the field Assigned value takes place, no matter the logic in the RT-XSG model.
• Warning: The assigned values for the analog outputs must be coherent with the voltage range in use. The hardware in use defines the voltage range, which may be alterable in RT-LAB. Example: When working in the +/-5 V range, the assigned output value should be within the range [-5, +5] V.
• Take value from RT-XSG model: typically the same behavior as before the feature DOV.
• Keep value unchanged from when the state was set: this behavior can be seen as creating a pause in the signal. Note that there could be discontinuities when changing the model’s state, meaning that pause is only internal to the FPGA and it is not linked with the data communicated with other systems. Per example, having a model that generates a sinus signal which is paused, then back to the Execute state, the signal can be at a different degree.
• Pause behavior: refers to a state of communication between the Target and RT-LAB software. This state is active when the model is in pause and the application has not crashed.
• Reset behavior: refers to a state of communication between the Target and RT-LAB software. This state is active when the model is neither in execution nor in pause.
• Assigned value: this field of the table can be graphically updated anytime, but the value can be ignored depending on the Pause behavior and Pause behavior selected.

Xilinx System Generator Block

Every Simulink model containing a block from Xilinx toolbox must contain a System Generator block.

It allows selecting different simulation parameters like the type of FPGA ship to program, the type of FPGA language to use, the clock frequency of the design between others.

When generating FPGA configuration files, the Synthesis Manager block takes care of the required settings, hence for this case, it is not necessary to set mask parameters.

Generate File

The Generate File button of the Synthesis Manager launches the generation process related to the checked check-box. Before clicking on that button, the user must select one of the Output files formats check-boxes:

OPBIN (OPAL-RT Bitstream File)

This check-box includes the following files plus a FSD file (used for FPGAScope feature). All these files will be compressed under a single file with the extension opbin.

BIT/BIN (Legacy FPGA Bitstream files)

Selecting that check-box and clicking on the Generate File button is the equivalent of the Generate Programming File button in the older RT-XSG’s versions.

CONF / OPAL (Legacy OPAL-RT Configuration files)

Check this checkbox so that the algorithm that automatically generates the configuration files required to link the FPGA and the mezzanine(s) is launched. Introduced in RT-XSG v3.1.8, this automatic generation of the configuration file requires that the user follows a set of design rules when preparing the model.

It is mandatory to use specified application blocks from RT-XSG library for the algorithm to identify the right configuration and interconnection within the model.

Subsection Rule

To identify a sub-section, a dedicated RT-XSG library is available. Use the block that corresponds to your application.

Tags Rule

This rule applies to the Goto and From blocks.  The matching Goto and From blocks must be in the model itself. That means you cannot use a From block that relates to a Goto which is under a block coming from a library.

The one exception in place is about the ModelSync tag that is under an RT-XSG block.