BLOCK
FPGA-BASED CIRCUIT
This component allows creating, editing, configuring and running an FPGA-based circuit. It provides access to the OPAL-RT Schematic Editor specifically designed to develop circuits for FPGA-based simulation. Multiple parameter sets can also be predefined to enable switching test cases while the simulation is running.
It is dedicated to the OpalBoards driver.
MASK AND PARAMETERS
General
Name: Dropdown menu to select the circuit to be simulated from the user database.
Refresh: This action updates the dropdown list of circuits available from the user database.
Edit: This action opens the selected circuit in the Schematic Editor.
Create new: This action creates a new circuit in the Schematic Editor.
Load circuit: This action loads the selected circuit into the Simulink block. The block is automatically redrawn, I/O and FPGA configuration files are updated. This action is required at every modification made in the Schematic editor to be applied to the Real Time simulation.
Load circuit results: This link will open in notepad the eHS Build Report that contains advanced circuit information such as effective and minimum achievable time step as well as all eHS input and generated outputs.
In case of error, the link will show you detailed error messages and give you access to error logs.
Source: If set to "Internal", choose from one of the predefined sets from the "Active Set" parameter.
If set to "External", the parameter set is controlled from an external Simulink source connected to the parameter_set_id block's inport.
Active Set: This action allows you to choose the active parameter set.
INPUTS, OUTPUTS AND SIGNALS AVAILABLE FOR MONITORING
The inputs and outputs of this model are generated dynamically depending on the sources, switches and measurements provided by the Schematic Editor circuit. Additionally, if the "Source" parameter is set to External, a parameter_set_id pin that allows controlling the parameter set from the CPU model is created.
Inputs
Controlled sources inputs: Drive the controlled current and controlled voltage sources of the Schematic Editor circuit.
Switches inputs: Control the switches of the Schematic Editor circuit.
Parameter set id: Only available if the "Source" parameter is set to "External". Allows the user to change the parameter set applied during the real time simulation.
Ouputs
Dynamcally generated: The outputs represent real time measurement values that were placed into the Schematic Editor circuit.
Note that eHS voltage and current measurements are averaged over a CPU model time step (a moving average function is performed on the FPGA device).
Exception: the measurements coming from machine blocks that are zero-hold sampled.
PARAMETER SET
Parameter set allows changing multiple circuit's component parameters during the simulation without having to reflash the firmware or stop and restart the simulation. Parameter sets' values, names and IDs can be defined in the Schematic Editor while editing the circuit.
TROUBLESHOOTING
If you see the message "OPAL-RT Unified Database is unavailable" beside the "Load circuit" button, verify your installation of the OPAL-RT Unified Database. If after clicking on either the "Edit" or "Create" button and the message "OPAL-RT Schematic Editor is unavailable" is displayed, verify your installation of the OPAL-RT Schematic Editor.
After clicking the "Load circuit" button, the configuration and binary files are automatically generated and placed in a folder called OpalBoardsAddons beside the model. Thus, when copying or changing the location of the model, do not forget to also move the OpalBoardsAddons folder.
In the case where loading a circuit succeeds, the 'More configuration details' link will open a detailed eHS Build Report that contains advanced circuit information such as effective and minimum achievable time-step and all eHS input and generated outputs.
In the case where loading a circuit fails, a notification message "An error occured during eHS configuration" appears. This message is clickable and a popup with more information about the failure is displayed.
MIGRATION TO NEW eHS SE OPALBOARDS DRIVER BLOCK
Since the version 2.11 of eFPGASIM, a new version of eHS OpalBoards driver block has been introduced to replace the old one.
It features a similar workflow to eHS Sfun driver block.
To update to this new block, follow the next steps :
- Edit the Simulink model and double-click on the old eHS SE OpalBoards Drivers block. A pop-up appears and propose you to migrate to the new eHS SE OpalBoards Drivers block.
- Click OK and wait for the migration to finish. The block should be replaced, and all pins should be reconnected. If there is an error at the migration see the steps below to migrate the block manually.
Save the model. - In RT-LAB, build your model.
- In the Probe Control, if there is a trigger signal name in the Data acquisition triggering group, select it again since some paths may have been updated.
- Load and Execute your model.
Troubleshooting
If the automatic migration doesn't work, follow these steps :
- Edit the Simulink model, and delete the old eHS SE OpalBoards Drivers block.
- In the library, search for the eHS SE OpalBaords Drivers, that is the new version of the block. Add it to your model.
- Access the mask and load the circuit needed :
- Reconnect all the pins and save your model
- In order to align all the new connections with RT-LAB, you need to copy a python script in the folder where your Simulink model is located. The python script is provided in the eFPGASIM install folder : "eFPGASIM/<v2.11.X>/Common/bin/OpalBoardsMigration/host_postcompile.py".
- Go back to step (c) above.
If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.