The following section shows the relationship between the I/O blocks in the RT-LAB model and the signal conditioning modules installed on the OP4512 simulator.
They are divided by groups and sections, and each is clearly identified in the illustrations.
The following I/O block mapping is provided with your system. It shows the specific pin assignment on standard DB37 or, DB9 connectors for the system and bitstream delivered.
Nomenclature correspondence between Simulink I/O blocks and OP4512 I/Os | |
Simulink blocks I/O nomenclature | OP4512 I/O ID nomenclature |
Slot (1, 2 or 3) | Slot/Group (1, 2 or 3) |
Module (A, B or C) | Section (A, B or C) |
Subsection 1 (SS1) | Pin ID 0 to 7 |
Subsection 2 (SS2) | Pin ID 8 to 15 |
Subsection 3 (SS3) | Pin ID 16 to 23 |
Subsection 4 (SS4) | Pin ID 24 to 31 |
The RT-LAB’s Simulink blocks used to access the OP4512 simulator I/Os use the following ID nomenclature:
SlotX.ModuleY.SubSectionZ.
To map the Simulink ID to the physical I/Os in the OP4512 (rear panel), the user is advised to use the nomenclature correspondence in the table above.
For example, in Simulink, Slot1. ModuleA. Subsection3 is equivalent to Group1.A.(16-23) on the OP4512 simulator.
The illustration below shows the arrangement of the subsections of signals for the DB37 and the DB9 connectors.
