In ARTEMiS v7, 2-level inverter (2LI) can be compensated ’inline’ in SSN, which results in a compensated simulation similar to the well-known TSB of OPAL-RT but without the internal delays associated with TSB.
See the online demo ssn_itsb_2levelvsc_hvdclink.mdl for more details.
Note: IVIC does not work for 3-level NPC inverters (3LNPCI). However, there is a demo called ThreeLevelInverter_IVIC_RTE2.mdl that use IVIC method in a surrogate circuit of the 3LNPCI.