In this section, SSN is used to simulate in real-time a complete 12-pulse bipolar HVDC link with switched filter banks. This test model is a 2000 MW (500 kV, 2 kA at each pole) HVDC link used to transmit power from a 500 kV, 5000 MVA, 60 Hz network to a 345 kV, 10 000 MVA, 50 Hz network.

The rectifier and the inverter are 12-pulse converters and the link is bipolar. The rectifier and the inverter are interconnected through two 300 km distributed parameter lines using 0.5 H smoothing reactors.

The transformer tap changers are not simulated and fixed taps are assumed. Reactive power required by the converters is provided by a set of capacitor banks plus 11th, 13th and high pass filters for a total of 600 MVAr on each side.

These capacitors and filters can be switched; each station has 7 switched banks.

Below, the SSN state-space groups are indicated by the colors. Stations (with 2 poles each) on both sides of the lines are simulated on two different cores of the RT-LAB simulator.

The natural delay of transmission line enables this decoupling. Each station circuit, comprising the two 12-pulse rectifiers are each simulated with a single SSN solver instance, without decoupling delays.

See References for more details.

Simulation Results

As a test case, we made the DC-link energization. Then, when the DC-link reached its nominal current, we began to connect filter banks 1 to 6 at 0.4 sec. intervals, followed by simultaneous disconnection of all banks at 5 sec. As expected and shown below, each time a filter bank is put on-line, it provides the AC network reactive power, i.e., raises the AC voltage amplitude and DC-link controllers react by raising the firing angle to keep the DC-link current at the nominal level.

The SSN method implements the Inlined Thyristor Valve Compensation algorithm (ITVC). The ITVC method is used to maintain the simulation accuracy even when the thyristor switching occurs between time-steps. The figure below shows the effect of the ITVC algorithm: the jitter caused by the sampling of the thyristors gate signal by the fixed-time step simulation time frame is decreased by 50%. This simulation imprecision, with the ITVC algorithm, turned off, is caused by fixed-step sampling and would be similar in any fixed-step software like EMTP, PLECS or PSCAD. The figure also shows a very regular current pattern with ITVC in action.

Real-Time Simulation Speed

The bipolar HVDC link with switched filters can be simulated at a time step of 49 µs on 6 cores of a 3.3 GHz Xeon V2 (3 cores per station). Higher speed can be expected if Xeon V3 is used.