Block
Mask
Description
This block generates a synchronization pulse train with the specified period. The width of the pulse equals the FPGA board clock period, during which its output value is the unsigned integer '1'. Otherwise it is the unsigned integer '0'.
Parameters
| Period | The period of the pulse train, in seconds. |
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Inputs
None.
Outputs
This block has one output, corresponding to the pulse train signal. Its format is Ufix1_0.
Characteristics and Limitations
| Direct Feedthrough | NO |
|---|---|
| Discrete sample time | NO |
| XHP support | N/A |
| Work offline | NO |