The FPGA Acquisition module enables the monitoring of high-speed signals internal to an FPGA board connected to an OPAL-RT Simulator, acquired directly on FPGA at a rate faster than the simulation step. The acquisition is possible on signals on which a probe exists in the firmware. These probes are either inserted explicitely in the RT-XSG model, or added automatically during the FPGA configuration file generation.

The maximum number of probes in a system is set to 32, including the automatically placed probes and explicit probes such as the ones visible in this model.

Inserting probes on signals

A probe can be added on a signal by connecting a "RT-XSG Acquisition Probe" block to that signal. The probe can be connected to an isolated signal, or to a FLWS Bus, enabling many signal to be monitored on a single probe.

Probe on an isolated signal

Inserting a probe on an isolated signal is made using a single Simulink line. The signal can be boolean, signed or unsigned fixed-point, or floating point. The maximum number of bits of the signal on which a probe is placed is 32.

Probe on a FLWS bus

Inserting a probe on an FLWS Bus is an advanced feature, and is made using a single Simulink line. The FLWS Bus should be created using the "FLWS_Bus_Pack" block. The maximum number of bits of the data of that bus is 32. The maximum depth of a FLWS frame on the bus is 256. Refer to the RT-XSG Acquisition Probe block for more information on how to describe the content of the FLWS frame.

Using automatically inserted probes

During the generation of the FPGA configuration file, probes will be added automatically on all analog and digital IO interfaces, as well as on signals from library blocks on which a probe has been placed.