Field Programmable Gate Arrays (FPGAs)

An FPGA is a programmable logic semiconductor device. Depending on the device model, it includes a certain number of programmable logic blocks and built-in functions. Many devices, including all OPAL-RT supported devices, are fully reconfigurable, enabling the user to sequentially perform any number of custom processing on the target platform.

RT-XSG Compatible Software

MATLAB/Simulink

MATLAB is a technical computing software package that integrates programming, calculation, and visualization. MATLAB also includes Simulink; this software package is discussed below. As RT-LAB and RT-XSG work in conjunction with this environment to define models, the user must be familiar with aspects of MATLAB as related to Simulink.

Simulink is a software package that enables modeling, simulation, and analysis of dynamic systems.

Models are described graphically, following a precise format based on a library of blocks. RT-XSG uses Simulink to define models that will be converted into configuration data for the targeted platform. It is expected that you have a clear understanding of Simulink operation, particularly regarding the model definition and the model various simulation parameters.

Xilinx Vivado Design Suite

Xilinx, Inc. is one of the world's major FPGA vendors. The Vivado Design Suite is a complete set of tools designed by Xilinx, Inc. to access, manage and generate the configuration data for their FPGAs. From within MATLAB/Simulink, the System Generator for DSP toolbox, also designed by Xilinx, Inc. gives access to a block set suited for implementation on an FPGA. It is assumed that the reader is familiar with the Xilinx System Generator for the DSP toolbox. Please refer to the System Generator for DSP User Guide and introductory tutorials for more information on this toolbox.

Although the user does not have to access them manually, many other components from the Vivado Design suite are indirectly called from both the System Generator for DSP and RT-XSG toolboxes. Please refer to the Vivado Design Suite documentation for information on each specific component.

Some of the supported platforms enable the creation of VHDL-only model descriptions. This configuration does not require MATLAB/Simulink as the configuration data generation is performed from within the Vivado Design Suite Project Navigator.  Detailed information on the use of this feature can be found in the specific platform RT-XSG documentation.

OPAL-RT Technologies Simulation Platforms

RT-LAB is a distributed real-time platform that facilitates the design process for engineering systems by allowing engineers to transform their Simulink dynamic models to real-time to hardware-in-the-loop simulations in a very short time at a low cost. Its scalability allows the developer to add compute power where and when needed.

It is flexible enough to be applied to the most complex simulation and control problem, whether it is for real-time hardware-in-the-loop applications or for speeding up model execution, control, and test.

RT-LAB provides tools for running simulations of highly complex models on a network of distributed run-time targets, communicating via ultra-low-latency technologies, in order to achieve the required performance. In addition, RT-LAB’s modular design enables the delivery of economical systems by supplying only the modules needed by the application in order to minimize computational requirements and meet customers’ price targets. This is essential for high-volume embedded applications.

The RT-XSG toolbox incorporates features to communicate at very high speeds with an RT-LAB model running in real-time.

The same architecture has been maintained for simulation using the HYPERSIM platforms. The bitstreams generated from RT-XSG can thus be used either in RT-LAB or HYPERSIM simulations. 

Introduction to the RT-XSG Hardware I/O Interfaces

A general data processing block diagram is illustrated in the following figure. The role of the RT-XSG toolbox is to provide the user with all the facilities necessary to feed the custom processing block with appropriate data, and to send the generated outputs to an appropriate target. In the following figure, these roles are symbolized by the two bold arrows.

The Input and Output can be implemented as needed by the application.

As examples, consider the four following cases:

• Direct input and monitoring devices, as external signal generators and oscilloscopes, respectively;
• In a hardware-in-the-loop simulation, outputs are used outside the box to generate the inputs directly by the hardware under test;
• In an FPGA-accelerated simulation, as when RT-XSG is used in conjunction with RT-LAB, the Custom processing block is used to offload part of the processing from the software processor onto the FPGA board. In this case, inputs come from the processor, and the outputs loop back to the same software model;
• Any combination of the above.

The type of input/output channel configuration is application-specific. Nevertheless, the maximum channel count is platform-dependent and is indicated in the documentation of the hardware platform selected.

RT-XSG FPGA Model Creation Paradigm

In the above figure, the Custom Processing block is designed by the user. It is often referred to as the User model.

For simplicity purposes, some structural and technical features are transparent from the user when working with the RT-XSG toolbox. Specifically, the User model signals are attached to a base configuration, which is the top-level hierarchical entity of the reprogrammable device and is invisible to the user.

The base configuration serves as an interface from the user model to the outside world (i.e. the components and ports on the target platform outside the programmable device). It manages the signal routing and I/O configuration compatibility with the user model and high-speed bidirectional communication with the real-time model.

The RT-XSG toolbox provides a series of block libraries that give access to a variety of analog and digital I/O interfaces, along with blocks that enable the transfer of digital signals to and from an RT-LAB simulation model in real-time. The toolbox facilitates interface management so that the user can concentrate on the algorithmic processing part of the design.