Location
This example model can be found in the software under the category "ABC" with the file name "ABC.ecf".
Description
This example shows how to simulate a four terminal DC grid power system with several MMC converters, all simulated on CPUs with controllers inside the model.
The number of cell per arms is moderate in this demo (=50). For cases with much higher cell counts, up to 512 per arm, it is recommended to model the MMC inverters on FPGA.
The model has a similar grid configuration as BM1 in Cigre B4-72. The dc voltage is controlled by T2. The other terminals adopts PQ control. See [1] for further details.
Note that this demo requires Opal-RT MMC blockset to be installed.
Simulation and Results
References
[1] C. Dufour, W. Li, X. Xiao, J.-N. Paquin, J. Belanger, "Fault studies of MMC-HVDC links using FPGA and CPU on a real-time simulator with iteration capability", 11th International Conference on Compatibility, Power Electronics and Power Engineering (IEEE CPE-POWERENG 2017), Cadiz, Spain, April 4-6, 2017.