Vivado Debug Core Block in FPGA Model

• For users of Xilinx Vivado 2017.4, put debug core block in FPGA model, name it as core 0, use the port tabs to connect the signals that need to be monitored, name them with meaningful names.
• Debug core block is in “RT XSG Tools” library.
• Maximum one Vivado ILA Debug Core block in a FPGA model.
• Maximum 1024 signals can be connected to the debug core block.
• Each signal should not exceed 4096 bits. Otherwise, the bitstream compilation will fail without a meaningful error message.
• The names of debugging signals plus the model’s name and subsystem names cannot exceed 260 characters.

• Click on the block Vivado ILA Debug Core, a window pops up, users can set parameters of the chipscope there.
• Vivado Parameters tab
  
  • Depth: the number of FPGA time steps to be contained in the chipscope, note: the depth will take FPGA resources, so it’s supposed to select a reasonable number.
  • Basic capture control mode: keep it as default, checked.
  • Advanced Trigger: keep it as default, checked.
  • Input pipe stages: keep it as default, 0
  • Match units per probe: keep it as default, 2.

• Probes tab
  
  • The signals which are connected to the debug core and their dimensions will be shown in this tab.
  • Note: the number of characters in each name cannot exceed 260
• Advanced Settings tab: it defines the default ports which is already configured in the block, keep this tab as default

• Generate bitstream using the FPGA model containing debug core and ports blocks.
• Run model in real time with bitstream loaded in FPGA.
• Use JTAG chain to connect the FPGA and user’s console computer.
• In console computer, launch Vivado from Windows start menu.

• Once Vivado is open, chose Open Hardware Manager

• Click Open target then select Auto Connect to connect the FPGA

Hardware Manager Window

• Hardware manager shows as follow once the hardware is detected:

• Specify the probes file (. ltx file matching the bitstream) to have the list of signals to be monitored.
• The . ltx file is generated along with the bitstream under the model folder.
• The . ltx file has the same name of the bitstream.

• Click ok, then click on fresh, the list of signals will pop up.

• Click ok, then click on fresh, the list of signals will pop up.

• The signals’ names should match the port tabs names for debug core.

Acquisition of the Signals

• Run without condition: Click on Run trigger for this ILA core button to have the signals waveform

• Run with condition: Users can set the triggering condition to have the moment when it’s met, then use Run trigger for this ILA core button to have the waveforms. The red line with letter T in the window is the triggered moment.

• Run with multiple conditions: Users can set multiple triggering conditions and the logic among them to have the moment when it’s met, then use Run trigger for this ILA core button to have the waveforms.

• Delete trigger conditions: Users can right click on the conditions and select ‘Remove’ to delete conditions

• Use Settings hw_ila_1 tab to set the capture mode e.g. capture mode, number of windows, window data depth, trigger position in window

• Capture mode: Always as default
• Number of windows: users can set how many windows of the triggering signal
• Window data depth: can be less or equal to the depth set in the debug core
• Trigger position in window: users can set at which position the trigger is made and shown in the window

Display of the Signals in Real-Time Simulation

• Users can choose the proper format to display the signals

• Users can choose different colors to highlight the signals

• Users can create new virtual bus by slicing bits from the existing bus

• Users can zoom in or out the waveforms
• Add markers to the waveforms
• More information about each button appears when the mouse hovers over the buttons