List of Abbreviation and Acronym

• CPU Central Processing Unit
• Eof End of frame
• PGA Field Programmable Gate Array
• HIL Hardware in the Loop
• HVAC High Voltage Alternating Current
• HVDC High Voltage Direct Current
• MMC Modular Multilevel Converter
• PWM Pulse Width Modulation
• PU per unit
• RCP Rapid Control Prototyping
• SI Système international International System of Units)
• SFP Small Form factor Pluggable
• SPF Single Precision F loating point
• SM Submodule
  
  • CDSM Clamped Double Submodule
  • FBSM Full Bridge Submodule
  • HBSM Half Bridge Submodule
  • T-SM T-type Submodule
• STATCOM Static Synchronous Compensator
• VBC Voltage Balancing Control

Nomenclature

• Ts ; Tcpu Time step in CPU model
• Tfpga Time step (Calculation cycle) in FPGA model
• Tclk FPGA clock time, normally 5ns or 10ns
• Vcap Submodule Capacitor Voltage
• Vdc dc bus pole to pole voltage

Outline

• Software and versions
• FPGA model h ierarchy
• IO blocks: DataIN , LoadIN , DataOUT
• MMC subsystem
  
  • Smsetup
  • MMC
  • Control
  • Connector

Typical Applications of MMC FPGA Models

• Preparing the firmware for different FPGA platforms (OP7020, OP5607, OP5700, or OP45x0)
• Configuring different number of valves simulated on one FPGA
• Implementing customized communication protocol to connect the controller under test
• Implementing customized valve balancing control algorithm

Software and Versions (for Xilinx Vivado)

• Matlab /Simulink Matlab 2016b: 64 bit recommended
• Xilinx Design tools: Vivado 2017.4 or above
• RT XSG: Version v3.1.8.105 or above
• MMC: V1.0

MMC FPGA Model at a Glance

Model Description

• Data in: receives data from CPU to FPGA every Ts
• Load in: receives system parameters from CPU to FPGA when parameters change
• DATA out: transfers data from FPGA to CPU every Ts
• Other models: MMC model can work with other models, such as IO or eHS
• MMC: simulates 6 valve converters. One FPGA could have multiple converters. Each contains:
  
  • controller: including VBC and pulse generator.
  • valve: MMC valve model (series connected SM).
  • connector: SFP driver and data format conversion between controller/valve and SFP blocks.

Model Hierarchy

Communications Between FPGA and CPU

• Data in: receiving signals from CPU, updated at every Ts
  
  • MMC Valve currents
  • Voltage reference
  • Gating signals
• Load-in: receiving system parameters from CPU, at model initialization or parameter change with lower update rate(i.e. whenever parameter changes).
  
  • MMC configurations
• DATA out : transfers signals to CPU, updated at every CPU time step
  
  • MMC valve voltages
  • MMC/control measuring and monitoring info
  • Capacitor voltages and SM states
• Above 3 blocks from RT XSG library. (or type rtxsg_communication ” in command windows).
• Each block has maximum 32 ports to connect to FPGA models. More info by clicking the “help” button in the block mask.

DataIN Port Description

• DataIN port 1: SM selection for fault . Receive 4 ufix32.0 data from CPU defining 4 SM selections. Please refer to help of CPU “SM sel ”
• DataIN port 2: valve current . Receive 9 data. 1 st 3 data for internal use. Next 6 SPF format data from CPU for 6 valve currents in Amp (SI value) value). Following into o1 as positive direction. Please refer to the help of MMC valve block in cpu
• DataIN port 3: pulse enable & Vref /gating signals. 1 st 3 data for internal use. 4 th data is pulse enable & G5 signals. Other data are either for Vref (fix24.23, 6 data for 6 valves) if in CPU model “MMC parameter controller gating signal from”= “ VBC ”, or gating signals (32bit, # of data determined on CPU model) otherwise.
• All 3 ports are in “ Async ” & “with start of frame”
• If more than 1 converter in FPGA, DataIN port 1 (SM selection) is for all converter. Each converter has 2 DataIN ports (“valve current” & “pulse enable & Vref /gating signals).

LoadIN Port Description

• LoadIN port 1: MMC parameter . Receive 24 32bit data from CPU for MMC parameters. Please refer to the help of MMC parameter block in cpu
• LoadIN port 2: CR discrepancy . Receive data from CPU for MMC SM capacitance and discharge resistance discrepancy.
• Above ports are in “ Async ” & “with start of frame”
• If more than 1 converter in FPGA, Each converter has 2 LoadIN ports.

DataOut Port Description

• DataOut port 1: valve voltage Vmmc . Send to CPU 12 Vmmc in Volt (SPF format)
• DataOut port 2: capacitor voltage & SM states. 6* Nvc 32 bit data for Vcap and optional Nvc 32 bit data for SM states. one 32 bit data for 2 Vcap (fix16.13) or 2 SM states (16bit). Nvc is defined in CPU model “MMC parameter scope SM number for display ” for eMEGAsim model, is equal 5 in Hypersim
• DataOut port 3: measuring & monitoring info . Send 19 32 bit measuring & monitoring info data to CPU.
• Above ports are in FIFO mode. Port 1 has “external data sync signal”; Port2& 3 doesn’t have “ external data sync signal
• If more than 1 converter in FPGA, each converter uses 3 DataOut ports.

Inside MMC Subsystem

• Internal use: for developer use
• S1: 6 valve converter model
• One can have multiple converters in 1 FPGA, e.g. S1, S2, …
• Number of converters is limited by license and FPGA resource

Inside Converter Subsystem

Smsetup Subsystem

Smsetup Block

• Smsetup block
  
  • reading all parameters and input from CPU;
  • packing data for inputs of downstream blocks
  • Generating timing reference and other auxiliary signals used by other blocks
• 3 outputs:
  
  • timing: timing reference and other auxiliary signals
  • gCPU : gating signal from
  • ref: Vref from CPU

MMC Valve Model Timing Reference

• Each MMC valve model has 4 identical SM calculation function.
  
  • 1 function handles 1 HB/FB SM (1 capacitor).
  • 2 functions together handles 1 CD/T SM (2 capacitors).
• Function works as pipeline. MMC valve model handles 4 HB/FB SM (or 4 capacitors) at each FPGA clock ( Tclk
• For a valve with n HB/FB SM (or SM with total n capacitors ), Valve model need minimum ceil( n /4) number of Tclk to handle all SM in valve, which also defined as calculation cycle ( Tfpga Example, a valve has 10 HBSM and 20 FBSM, Tfpga_min = ceil((10+20)/ Tclk = Tclk or 40ns if 1 FPGA clock is 5ns).

Smsetup Block: Output Timing

• Output “timing”: connected to valve model
  
  • vlv (52 bit): internal use (MMC valve model);
  • pre SMind (8 bit): reference index;
  • pre GPind (2 bit ): reference group index;
  • pre Cact (4 bit ): SM(capacitor) valid bits;
  • pre GReof (1 bit ): end of frame(cycle) signal;
  • Gind : internal
  • datadisc dis(0~5) (20 bit): RC parameter discrepancy.

MMC Valve Model Timing Reference

• SMind : counter signal, increasing by 1 @ each FPGA clock and wrapping to 0 when reach (Ncc 1). Ncc is calculation cycle in terms of number of FPGA clock.
• GPind : counter signal, increasing by 1 @ each calculation cycle (from SMind =0 to Ncc 1 )and wrapping to 0 when reach 3.
• Cact : SM valid bit, 4 bits for 4 functions. 1 if function is handling a SM at current FPGA clock.
• GReof : end of frame(cycle) signal. 1 if handling last SM at current FPGA clock.
• Above 4 signals are timing references for other signals (e.g. inputs and outputs of pipeline functions).
• Example: 1 valve has 10 HBSM and 20 FBSM, Ncc = 8 FPGA clock.

• For SMind =0~6, 4 function are handling 4 SM. Thus Cact =1111|b
• For SMind =7, only 2 function are handling last 2 SM. Thus C act =0011|b; and GReof=1.
• calculation cycle can be set more than its minimum value. Example: 1 valve has 10 HBSM and 20 FBSM, Ncc = 20 FPGA clock.

• SMind increases from 0 to 19 and ramps to 0.
• For SMind =0~6, 4 functions are handling 4 SM. Thus C act =1111|b
• For SMind =7, only 2 functions are handling last 2 SM. Thus C act =0011|b ; and GReof =1
• For SMind =7~19, 4 functions are idle: Cact =0000|b

Smsetup Block: Output gCPU

• Output “ gCPU gating signal from CPU, connected to connector
  
  • cmd i i =(0~ 32 bit): gating signals of 8SM (SM(8n)~SM(8n+7)) Each SM has 4 bits, SM in ascending order, e.g. SM(8n): bit[3:0]; SM(8n+1): bit[7:4];…; SM(8n+7): bit [31:28]; In each SM, G1:bit[0], G2:bit[1], G3:bit[2], G4:bit[3
  • vld (1 bit): valid bit of cmd i
  • eof (32 bit): end of frame signal;
  • nbc (10 bit): total number of cap in a valve;
  • gg (5 bit): extra gating signal info
    
    • pulse enable(bit[0]);
    • G5 of CDSM (bit[1]);
    • force bit of HBSM (bit[2]) 2]);
    • bit[3:4] reserved

Smsetup Block: Output Ref

• Output “ref”: mmc voltage reference, connected to controller subsystem “ctrl”
  
  • conf (64 bit): parameters ; part of “ctrl” input config
  • ref (192 bit ): voltage reference for 6 valves ; 32bit each for each valve. lower bits for lower numbered valve, e.g., bit[31:0] for valve 0. In 32 bit, lower 24 bit used (Fix24.23).

MMC Valve Model

• Routing subsystem: input signal routing
• vlv (0~5 ): 6 MMC valves

• Buffer: gating signal buffer
• Grepacking : repacking gating signal at specific timing sequence
• Protection: in SM protection logic
• MMC: valve model
• Vcrepack : repacking output Vcap for downstream blocks

Gating Signal Buffer in Valve Model

• Input
  
  • Wdata : gating signal (from Connector G_routing")
  • Rset : signals containing timing info to read gating signals from buffer (from “ Smsetup")
• Output “ Rdata ”: gating signal sent to valve model
• RAM0,RAM1: two double buffers for gating signals

Wdata: gating signal (from Connector G_routing

• Eof (1 bit): “end of frame” bit.
• Vld0(1 bit ): valid bit for cmd0.
• Vld1(1 bit ): valid bit for cmd1.
• Cmd0,1(64 bit): gating signals for 4SM, 16bit per SM.

lower bits for lower numbered SM, e.g. cmd [15:0] for SM(8n), cmd [31:16] for SM(8n+

• cmd0 for SM(8n+[0~3]), n increases by 1 at vld0=1 and reset by Eof
• cmd1 for SM(8n+[ 3~7]), n increases by 1 at vld1=1 and reset by Eof

2 RAMs for buffer of gating signal. Each RAM can save gating signal of 4 SM at each FPGA clock.

• RAM0 saves gating signal of SM(8n+[0~3]) from cmd0;
• RAM1 saves gating signal of SM(8n+[3~7]) from cmd1

Purpose of having 2 RAMs is to handle different protocol, e.g.

• gating signal of 8 SM sent in one FPGA clock;
• gating signal of 4 SM sent in one FPGA clock;

Example 1: gating signal of 8 SM sent in 1 FPGA clock from protocol

• 2 valid bits (vld0 & vld1) is synchronous;
• at one FPGA clock, signals of 8 SM is saved in 2 RAM when valid bit is 1.

Example 2: gating signal of 4 SM sent in 1 FPGA clock from protocol

• 2 valid bits (vld0 & vld1) is not synchronous
• at one FPGA clock, signals of 4 SM is saved in 1 RAM of which corresponding valid bit is 1

Protection in Valve Model

• Input
• Gatein : input gating signal of 4 SM
• statep : SM state
• Output:
• gateout : output gating signal for valve model
• Protection(0~3): in SM protection logic * 4

MMC Valve Blackbox

• 3 inputs
  
  • gate (64 bit )): gating signals for 4 16bit per SM. From “protection”.
  • Para ( 566 bit): parameter and config
  • Current (32 bit): valve current (SPF)
• 3 outputs
  
  • Vs (64 bit): valve voltages
  • Info (64 bit ): measuring and monitoring info
  • state(320 bit)bit): SM info for 4 SM, 80 bit per SM. For
    
    • Vcpu (0~3) (16 bit): Vcap pu value, Fix16.13
    • Vcap (0~3) (32 bit): Vcap in Volt, SPF format
    • status(0~3) 3)(16 bit)bit): SM states
    • gate(0~3) (16 bit ): gating signals

MMC Valve Model

• For each SM:
  
  • gating signal (16 bits)

• SM state (16 bits)

MMC Valve Model: Input “Gate”

• gate (64 bit): gating signals, from “protection”
  
  • 64 bit for 4 SM, 16 bit per SM
  • Lower numbered group of 16 bit for lower numbered SM;
  • Input for 4 SM at every FPGA clock;
  • First 4 SM at FPGA clock that SMind =5

MMC Valve Model: Output “State”

• state(192 bit): SM info
• Output info for 4 SM at every FPGA clock;
• 3 signals (80 bit) per SM, (refers to “naming” block)
  
  • Vcpu (16 bit, [15:0 ]): Vcap in PU, Fix16.13;
  • Vc (32 bit, [47:16]): Vcap in valt , SPF
  • status (16 bit, [63:48]): SM states
  • gate (16 bit, [79:64]): display of gating signals
• First 4 SM at SMind = 2.

MMC Valve Model: Output “Vs”

Valve voltages Vs (64 bit)

• two equivalent valve voltages for both current directions, in volt (SPF format)
• Values are sent to CPU at every Tcpu

Vcrepack Block

Vcrepack: repacking output Vcap for “connecter” block

• Input from MMC: Vcap of 4 SM per FPGA clock
• Output to protocol: Vcap of 2 SM per FPGA clock

• 3 Inputs
  
  • SMind & GPind : timing reference signals
  • stateP : Vcap and SM states from valve model output
• 1 Output: Vcdata , Vcap and SM states in re arranged timing sequence
  
  • vc (32 bit)bit): Vcap for 2 SM (SM(2n,2n+1)) if address=n . low 16 bit for SM(2n), high 16 bit for SM(2n+1). Format Fix16.13.
  • stat(32 bit )): SM states ( SM(2n,2n+1
  • valid(1 bit)bit): valid bits
  • address(9 bit): address

Input and output timing sequence:

• Input from MMC: Vcap of 4 SM per FPGA clock
• Output to protocol: Vcap of 2 SM per FPGA clock

Controller Subsystem

• Ctrl block reads Vmmc reference from CPU and output gating signals to MMC valve subsystem.
• Routing subsystem: input signal routing
• Ctrl(0~5): 6 valve control, each includes gating signal generation and VBC

Ctrl Blackbox

5 inputs

• Config (127 bit): parameters:
  
  • bit0(LSB): modelsync
  • bit 103:94 ]]: (total Capacitor nub 1)
  • others: internal use
• ref ( 32 bit ):lower 24 bit valid for voltage reference (Fix24.23).
• Vcdatain : 3 signals of Vcap to be written in RAM
  
  • v (32 bit ): Vcap (Fix16.13), lower 16bit for SM(2n ) & high 16bit for SM(2n+1 ) if valid bit=1, address=n
  • valid(1 bit ): valid bit
  • addr (9 bit ): address of Vcap
• cnt (9 bit ): address to read Vcap from RAM. 2* Vcap at a time.
• Current (32 bit): valve current (SPF format)

2 outputs

• ctlout (34 bit )): parameters
  
  • bit0: valid bit
  • bit1: “end of frame” bit.
  • bit[31:0]: gating signals
  • of 8SM(SM(8n)~SM(8n+7)).
  • Each SM has 4 bits , SM in ascending order, e.g.
  • SM(8n): bit[3:0]; SM(8n+1): bit[7:4];…; SM(8n+7 ): bit [31:
  • In each SM, G1:bit[0 ], G2:bit[1], G3:bit[2], G4:bit[3].
• Info (32 bit): for monitoring info sent to CPU

Connector Susbsystem

Signals in FPGA

• Traffic in 2 directions contains different signals
  
  • Measurements in path from valve to controller ( outbound direction)
  • Commands in path from controller to valve (inbound direction)
• Same signal at different locations have different data format and timing
  
  • MMC, control, & SFP

• Traffic in 2 directions contains different signals
  
  • Measurements in path from valve to controller ( outbound direction)
  • Commands in path from controller to valve (inbound direction)
• Same signal at different locations have different data format and timing
  
  • MMC, control, & SFP
• Protocol may vary in different projects
  
  • Number of fiber optic
  • SFP (optical modular transceiver) specs
  • Protocol: Aurora, Gigabit Ethernet
  • Protocol at data application layer
    
    • Interval between packets
    • How many & what signals being sent, in what sequence & data format
• Connector block may change to respect actual situation if necessary

Connector Subsystem

• Different data format and timing at different locations
• Buffer is used for data format and timing conversion
• Buffer contains
  
  • RAM or register cluster: signal storage
  • Logic: format and timing conversion

• MMC_out: packaging MMC output into packets sent to control
• SFP_MMC: SFP driver at valve side (sending valve measurement & receiving control command)
• Meas_routing: routing & unpacking received MMC measurement packet for control input
• Ctl_out: packaging control output into packets sent to MMC
• SFP_ctl: SFP driver at control side (sending control command & receiving valve measurement)
• G_routing: routing & unpacking received control command packet for valve input
• SFP_dummy: dummy subsystem to replace SFP_MMC or SFP_ctl if SFP driver is not used

MMC_out Block

• MMC_out block:
  
  • reads data (valve measurements) from valve model output,
  • packs and outputs data in format & timing as defined in protocol.
• Two subsystems:
  
  • Rambuffer: Ram as buffer
  • TXinterface: generic transmission interface, defining protocol timing.

• Rambuffer: Ram as buffer
  
  • Data from valve are written to Ram according to timing defined by valve model.
  • Data to protocol are read from Ram according to timing defined by protocol
  • Data format are converted if necessary
  • Normally number of Ram is same as number of fiber optic in one valve.

• TXinterface: example of standard FPGA model for demo bitstream

• Example of standard FPGA model for demo bitstream
  
  • One fiber optic (channel) for 1 valve (6 for a converter)
  • Each packet sending Nmeas =(floor(n/2)+2) number of 32 bit data, n is number of capacitor in a valve.
  • 1 st data is current in pu using lower 28 bits (FIX28.24)
  • Other data are capacitor voltages. 1 data for 2* Vcap (Fix16.13). Lower 16 bit for lower numbered capacitor.

TxInterface Block

• TxInterface : packaging data according to protocol
• One TxInterface block For each fiber optic (channel)

5 inputs

• Enable (1 bit ) & TX_READY (1 bit): signals from SFP, both = 1 in normal conditions. If packets are directly sent to internal control, both =1 to mimic SFP signals in normal condition.
• Sending period (16 bit )): interval between two packets, in terms of number of FPGA clock.
• NbrData (9 bit )): number of data in one
• Din(32 bit )): data being sent in packet. It should input i th data if output TX_DATA_INDEX is i at previous FPGA clock.

2 outputs

• TX_DATA_INDEX (9 bit): counter signal counting from 0 to Nmeas every “Sending period” when both “Enable ” and “TX_READY” are 1. Nmeas is number of data in a packet.
• TX: data packet being sent to controller.
  
  • vld (1 bit): valid bit
  • data(32 bit): data
  • eof (1 bit): end of frame signal

• Example : 7 HBSM, Sending period=20, and always Enable=1, TX_READY=1.
• Nmeas =5 data in 1 packet. Input NbrData =
• if TX_DATA_INDEX is i , “din ” is ready to receive i th data after 1 FPGA clock
• TX_DATA_INDEX increases from 0 to 5 every 20 FPGA cycles. TX_DATA_INDEX can serve as data address in RAM.

• When TX_DATA_INDEX keeps 0, 1 st data sent “din” might be updated.

• How to interface valve model output ( Vcap , valve current) with TxInterface input “din”? (signal timing is different in two subsystems)
• Answer: RAM buffer

• How to interface valve model output ( Vcap , valve current) with TxInterface input “din”? (signal timing is different in two subsystems)
• Answer: RAM buffer and selector

SFP Subsystems

• SFP_MMC for MMC valve side, SFP_ctl for controller side:
  
  • Including SFP driver.
  • Sending & receiving data packets as flowing into & out of SFP.
• Example of standard FPGA model for demo bitstream

• Example of standard FPGA model for demo bitstream
  
  • One fiber optic for 1 valve (6 for a converter);
  • In SFP_MMC or SFP_ctl block, 1 SFP driver block for 1 fiber optic (6 in a block);
  • GenericHighSpeedComm_Aurora_8B10B_7Series ” for SFP with Aurora protocol. Properly set parameters in mask.
  • Channel number corresponds to SFP port number in physical setup. Two blocks cannot have same Channel number.

SPF Driver Block

• SPF driver block:
• Receives data being sent out through fiber optic
• Output data being received through fiber optic
• Inputs/Outputs for data transfer
  
  • TX/RX_DATAVALID: valid bit
  • TX/RX_DATA: data being sent/received if valid bit is 1
  • TX/RX_LASTDATA: 1 if last data being sent/received or 0 otherwise.
• Other inputs/outputs
  
  • TX_ready, Lane_up, Channel_up: signals have to be 1 to be able to sent/receive data.

• For transferring data (d(0)~d(last)), timing of signals:
  
  • TX/RX_DATAVALID: valid bit
  • TX/RX_DATA: data being sent/received if valid bit is 1
  • TX/RX_LASTDATA: last data being sent/received

SFP_dummy Subsystem

• SFP_MMC and SFP_ctl blocks take FPGA resources.
• If only digital simulation required without using SFP/fiber optic , SFP_MMC and SFP_ctl blocks can be replaced by SFP_dummy block for special bitstream version to save FPGA resources.
• SFP_dummy does nothing but has output with same signal name, data type and dimension as SFP_MMC or SFP_ctl block to avoid data type or dimension error messages at model compilation.

meas_routing Subsystem

meas_routing Block

• meas_routing block:
  
  • routing i : Selects valve measurements source: from protocol SFP_ctl ) or internal connected ( MMC_out ).
  • interpt i :packs and outputs data in format as input of “ctrl”
• Example of standard FPGA model for demo bitstream
  
  • One data path for 1 fiber optic (6 in a block)

• meas_routing i : selects if valve measurements is from protocol (from SFP_ctl ) or internal connected (from MMC_out ).
• 3 Inputs
  
  • sel: selection
  • int: data from MMC_out block (directly from valve model)
  • ext: data from SFP_ctl block (through fiber optic)
• Output “out”: data from the selected source.
• int ”, ext ”, & “out” contains same signal type & dimension
  
  • Data(Ufix32.0): data
  • Vld (bool): valid bit
  • eof ( bool): end of frame signal

Interpt Block

• interpt i: packs and outputs data in format as input of “ctrl” model
• Output “ Vcdatain
  
  • Vcdatain (3 signals):
  • v (32 bit ): Vcap (Fix16.13
  • addr (9 bit ): address, starts with 0;
  • valid (1 bit ): valid bit;
• Current (32 bit): valve current (low 28 bit valid for Fix28.24)
• Eof (1 bit ): end of frame bit

Ctl_out Block

• Ctl_out block:
  
  • reads data (control command) from VBC output,
  • packs and outputs data in format as defined in protocol.
• Two subsystems:
  
  • Rambuffer: Ram as buffer
  • TXinterface: generic transmission interface, defining protocol timing

• Rambuffer: Ram as buffer
• Data from ctrl are written to Ram according to timing defined by ctrl model.
• Data to protocol are read from Ram according to timing defined by protocol
• Data format are converted if necessary
• Normally number of Ram is same as number of fiber optic in one valve.

Connector\MMC_out Block

• Example of standard FPGA model for demo bitstream
  
  • One fiber-optic (channel) for 1 valve (6 for a converter)
  • Each packet sending Ncmd =(floor(n/8)+1) number of 32 bit data, n is number of capacitor in a valve.
  • 1 data for 8*cap. Only G1~G4 are transferred. Bit[7:0]: G1; Bit[15:8]: G2; Bit[23:16]: G3; Bit[31:24]: G4.Lower bit for lower numbered capacitor.

TxInterface Block

• TxInterface (similar as in MMCout ): packaging & sending data to
• RAM buffer: interfacing VBC output with TxInterface input “din”.
• Command source selector: from embedded VBC or CPU.

g_routing Block

• g_routing block:
  
  • Selects command source: from protocol (SFP_MMC) or internal connected ctl_out ).
  • packs and outputs data in format as input of “valve” model.
• Example of standard FPGA model for demo bitstream
  
  • One data path for 1 fiber optic (6 in a block)

• g_routing block: selects command source & packs and outputs data
• Output “Gin”: (same format as input of valve
  
  • Cmd0(64 bit): gating signals for SM [0:3,8:11,16:19
  • Vld0 (1 bit): valid bit for SM[0:3,8:11,16:19
  • Cmd1(64 bit ): gating signals for SM [4:7,12:15,20:
  • Vld1 (1 bit): valid bit for SM [4:7,12:15,20:
  • Eof (1 bit): “end of frame” bit.
  • For Cmd0 and Cmd1, 4 SM at a time, 16bit per SM.

Connector

• In MMC projects, communication between valve & controller may different as example FGPA model, such as
  
  • measurements of 1 valves transferred by 2 fiber optic;
  • 6 valve currents are transferred in each fiber optic;
  • Voltages are transferred before current;
  • Each voltage uses 32 bits (1 data for 1 Vcap
  • Extra info, such as SM states, is transferred;…
• Logic in “Connector” blocks has to be modified accordingly:
  
  • Number of data paths accords to number of fiber optic.
  • Data packing/unpacking logic accords to protocol definition.
• "Connector” blocks outputs to “valve” and “control” subsystems should always accord to input of downstream subsystems.