To route physical IO (AI, AO, DI) to the eHS core during real-time simulation, an OPAL-RT Board must be created, configured, and assigned to an associated subsystem (i.e RT-LAB Model). If an OPAL-RT Board is not created and configured, the eHS running on the OP4200 will not be able to interact with physical IO. Follow the steps below to configure an OPAL-RT Board interface.
- To create a new OPAL-RT Board, right-click on the I/Os item and select New>New I/O. In the Add New I/O window, select OPAL-RT Board and provide an I/O name. Click Finish.
Note: The Boost and Two-Level example already contains a pre-configured OPAL-RT board so there is no need to create a new one.
- Double-click the OPAL-RT Board to open the OPAL-RT Board Configuration window. Set the Associated subsystem to the OP4200_eHSx32_Boost_and_TwoLevel_Inverter/SM_eHS. In addition, select the appropriate Bitstream configuration from the drop-down menu.
- With the above step complete, all the I/O supported by the firmware (defined by the Bitstream configuration) will be displayed to the left of the General tab. Each channel in each type of I/O board can be configured to meet the simulation requirements. For this example, the I/O has been pre-configured to meet the simulation requirements of the declared circuit model (Boost_and_2LvInverter_SPS.mdl).
- When all the I/O parameters of the simulation have been configured, save the configuration using the save button.
- After changing and saving the OPAL-RT Board configuration, it is necessary to recompile the CPU model by selecting Build the model from the Preparing and Compiling window. This allows RT-LAB to automatically detect the connections made between the model and the OPAL-RT Board.
- Configure the links between OPAL-RT Board and the CPU Model. To achieve this task, double-click Configuration from the Project Explorer tree.
- The displayed panel allows for connections to be made between the CPU Model and the IO data points (i.e. it provides links between the Real-Time controller and the FPGA). For instance, to create a connection between the PWM Out defined in the OPAL-RT Board and the Model, simply drag and drop the Frequency and Duty Cycle from Channel 0 of the OPAL-RT Board tree to the desired signal inputs of the eHS tree.
Note: In this particular example, the switches in the simulated circuit model are driven by the internal PWM generators available in the FPGA firmware. To route these PWM signals to the inputs of the eHS solver, a DIO loopback connection should be made between the DO and DI cassettes. Next, the OPAL-Board Configuration tab can be used to easily route the internal PWM signals to the digital outputs as demonstrated in the figure below.
