Large AC-DC-AC Drive with AFE Rectifier, Motor Drive Inverter and Paralleled TSB-RD Models

This circuit is an AC-DC-AC drive with an induction motor, based on a topology used by Rockwell. As in real life drives, the power level is scaled using parallel inverter building blocks and interphase inductance.

TSB and interpolation

TSB are interpolating inverters. Used in conjunction with RT-EVENTS modulator or with Time-Stamped Digital Inputs (digital input with 5-10ns event capture capability), TSBs and TSB-RDs compensate for the sampling effect of the simulator. Accuracy is excellent until Tpwm/Ts>10 (Ts is sample time of the simulator). Below this ratio, some accuracy is lost but the fundamental component of the modulation should stay accurate. In the demo model, we have Tpwm/Ts ratios of 13.3 and simulations are as accurate as if the ratio were >100 with standard (non-interpolating) simulation.

2-level TSB-RD characteristics

The inverters are simulated using TSB-RD (Time-Stamped Bridge with real-diodes) and have the following key characteristics:

Natural rectification and high-impedance capability due to the real diodes (i.e. real SPS diode). The snubber used in TSB-RD are real RC snubbers and are typically of much higher impedance than in the regular TSB models.
Deadtime supports lower than the simulation sample time. In this circuit, the deadtime is close to 4 µs while the simulation time step is 50 µs. This feature is NOT available in any native SPS switch model.
Parallel TSB capability: this feature may seem obvious but in real parallel drives like this one, the various inverters in parallel have slight delays in firing, which in turn can lead to uncharacteristic circulating currents. In this model, we added a 400 nanoseconds delay between the 2 motor inverters, creating a small current difference between the 2. Real controllers will shut down when this current is too high.

Figure 1: Complex AC-DC-AC induction motor drive with parallel 2-level inverters

Because each TSB-RD inverter has real SPS switch inside, SSN is required to separate these switches into different SSN groups and maintain real-time capability. DC-link has been separated with a delay as this is more efficient than SSN.

Figure 2: SSN and delay-based decoupling of the model