ARTEMiS Three-Level NPC Inverter Simulation with Compensation of Switching Events using Inlined Time-Stamped Bridge SSN

The circuit shows the capability of ARTEMiS-SSN to accurately simulate 3-level NPC Voltage Source Converter (VSC) circuits

ARTEMiS-SSN incorporates a novel interpolation algorithm for 2-level and 3-level inverters very similar to RTe-Drive Time-Stamped Bridge (TSB).

One main difference with TSB is that there is no decoupling delay between the inverter and the rest of the circuit.

In some circuits, a delay-free solution is important to obtain an accurate simulation at a relatively large time step. Without delays, this 'Inlined TSB' compensates for the output voltage and also the bridge input currents.

The interpolation method uses a signal that encodes rising edge with timestamps, falling edge with time stamps and in-step pulses (both positive and negative)

The image above explains the relation between the IGBT gate level in continuous time and the sampled RTE2 level (which varies from -1 to 2)

The model includes the required format conversion from standard RT-EVENTS signals.

Demonstration

In this demo, a 3-level NPC inverter is used to generate a 3-phase current into a load using PWM. The load has an optional neutral. Users can shut down the pulse and vary the modulation index from the Console.

In the simulation, the sample is 35µs, PWM frequency is 2 kHz. With the benefit of interpolation, the simulation shows current and voltage with negligible amplitude jitter.