Simulation of Small HVDC System with Nodal State-Space SSN and Inlined Thyristor Valve Compensation ITVC Algorithms

The circuit shows the capability of ARTEMiS to accurately simulate a circuit using the SSN and ITVC algorithms.

Demonstration

The small HVDC model has four SSN groups contoured by Nodal Interface Blocks (NIB). One group is made of the inductive 3-phase source that includes an AC-fault. The second group is composed of the switched filter bank (main capacitor plus 5th, 7th and high-pass harmonic filters. The 3rd group is made of the rectifier-side transformer and a 6-pulse thyristor valves group. The last group is made out of the complete inverter side plus line and rectifier smoothing reactor. On the above image, the SSN groups are circled in red.

Depending on their nature, the groups require different interface types: the inductance source, the converter, and inverter require a V-type Nodal Interface because they have inductive input while the filter bank requires an I-type Nodal interface because of its capacitive nature.

The groups are connected to a total of 4 nodal points defined by the SSN Nodal Interface Blocks. These NIBs are the nodes used in the admittance matrix of SSN.

SSN does not have any an a priori limit on the number of switches it can simulate in real-time

The system has a total of 12 switches. In standard ARTEMiS, there would be 2¹²=4096 state-space equations to precompute to allow real-time simulation. This is a rather large number of matrices and will require a lot of memory during the real-time simulation. One key aspect of the SSN algorithm is that it distributes the pre-calculation of state-space matrix sets across the groups. Therefore, the required memory is drastically diminished. In this small HVDC model, for example, there is a maximum of 64 matrices (for the 6-pulse converter) to be precomputed in one group. A nodal LU approach with on-line re-triangularization is used to find the simultaneous solution of all the groups, much like standard nodal approach (Dommel-type).

SSN Inlined Thyristor Valve Compensation (ITVC) algorithm

This model also shows the ability to compensate for thyristor valves switching effect using ARTEMiS-ITVC algorithm.

In the regular fixed-step simulation, sampling effects occur during the simulation of the switched converter. For example, if a thyristor firing signal occurs in the middle of a time step, it can only be taken into account at the next time step hit. This repetitive phenomenon typically causes uncharacteristic low-frequency jitter in the simulation results. If you removed the ARTEMiS GUIde and start the simulation with the native SPS solver, you will observe a small irregular variation of the DC-link current for example.

With the ITVC algorithm, this jitter is completely removed. To better observe the jitter, remove all faults from the model (by adding 100 sec to switching times) and zoom in on the Id current.

SSN group identification using tags and other useful information

The image also shows how to relate SSN groups in the diagram to the MATLAB listing. In the listing below, we see 'TAG' with the names used in the model. Other useful information is found in this listing such as the number of nodes, the required memory, the number of RLC elements and an estimation of the number of operations required by the SSN algorithm. These can be useful to optimize the SSN model.

• ARTEMIS-SSN:
  • Approximate memory required: 0.59939 Mb (including nodal matrix)
  • Estimated number of mult-add operations: 3400 (including LU factorization)
  • Estimated number of mult-add operations: 256 (best case without switches or variable admittance groups)
• SSN group info: 
  • Group 1 : 3 states, 7 inputs, 8 outputs, 2 switches.
  • Group 2: 21 states, 9 inputs, 6 outputs, 3 switches. TAG: capa
  • Group 3: 6 states, 7 inputs, 4 outputs, 1 switches. TAG: rect
  • Group 4: 12 states, 16 inputs, 18 outputs, 6 switches. TAG: xfo
• SSN nodal matrix is of rank 4 (0 % of zeros)
• ARTEMIS network information: the network contains 43 general electric nodes (RLC branches, sources, pi-line, etc..)