ARTEMiS-SSN Inlined Time-Stamped Bridge in 2-level VSC-based HVDC Applications Using IVIC Algorithm SSN

The circuit shows the capability of ARTEMiS-SSN to accurately simulate 2-level Voltage Source Converter (VSC)-HVDC circuits.

ARTEMiS-SSN incorporates a novel interpolation algorithm called Inlined Voltage Inverter Compensation (IVIC) for 2-level inverters very similar to switching-function Time-Stamped Bridge (TSB).

The main difference with TSB is that there is NO DECOUPLING DELAY between the inverter and the rest of the circuit as the inverter switches are fully embedded (or Inlined) in the system state-space equations.

Demonstration

In this VSC-HVDC demo, a delay-free solution is mandatory to obtain an accurate simulation at a relatively large time step. Also, not only the 'Inlined TSB' compensates for the output voltage, but it also compensates the bridge input current, a critical aspect in this demo.

In this demo, the sample is 20µs, PWM frequency is 1950 Hz and a dead time of 2 µ.s. is applied to the PWM firing.

The simulation shows current and voltage amplitudes have a negligible jitter with the IVIC algorithm (left scope) while regular SPS simulation (right scope) have the typical jitter caused by its inability to compensate for switching events occurring in the middle of simulation time steps.