Location

This example model can be found under the category Transportation with the file name FPGA-Based_PMSM_DRIVE.ecf, or, if you are using the OP4510 platform, FPGA-Based_PMSM_DRIVE_4510.ecf.

Description

The model developed in this project illustrates the closed-loop speed control of the FPGA-based Permanent Magnet Synchronous Machine (PMSM) interconnected with a two-level voltage source converter. The machine ratings and parameters are selected to represent an electric motor typically used in passenger electric vehicles.

This example is based on OPAL-RT's real-time simulators, which have CPUs and/or FPGAs as major processing units. Here, the plant model is built in the FPGA-based schematic circuit editor, the PMSM and the two-level converter is simulated on FPGA, while the controller is built in HYPERSIM, which runs on a CPU core at a time step of 50µs.

Model Parameters

S.No	Parameter	Value
1	Rated power of machine	75 kW
2	Rated speed	3000 rpm
3	Rated torque	200 N-m
4	Rated current of machine	200 A
5	Dc bus voltage	950 V
6	Switching frequency	20 kHz
7	Number of poles	12
8	Stator resistance	6.2 mΩ
9	D axis inductance (Ld)	1.034 mH
10	Q axis inductance (Ld)	1.034 mH
11	IGBT On-State Resistance [IGBT_Ron]	1 mΩ
12	IGBT Snubber Resistance [IGBT_Rs]	No snubber
13	IGBT Snubber Capacitance [IGBT_Cs]	No snubber
14	Machine Snubber R	1 kΩ
15	Machine Snubber C	100 nF
16	Inertia of the Machine	0.1863 Kg-m2

Controller Description

Field Oriented Control of the PMSM is implemented on the CPU, which runs at a sampling time of 25 microseconds. The control architecture is given in the figure below.

It has a standard outer loop speed control and inner loop current control. The transformation used is quadrature transformation with the d-axis aligned to the phase A axis (Original Park).

The OPAL-RT Board I/O interface is configured to generate PWM pulses for the converter. The modulating waves are clamped to a value between 0 and 1 to suit PWM configuration. The carrier frequency chosen here is 10 kHz and the exchange of information between the controller and plant happens via digital loop-back connections.

Machine generated currents, speed and theta information are routed to the controller as an input via the FPGA-based circuit component present in the HYPERSIM model.

Simulator setup

This example requires to set a digital loopback wire on the simulator between the Digital Inputs and Digital Outputs channels 0 to 15

Configuration and Interface

The plant model (PMSM_Drive_OP4510) built in the schematic editor is configured to read the PWM pulses from the Digital In card of OPAL-RT’s real-time simulator.

The following image illustrates the digital in configuration.

The simulator settings are configured by the user in the Schematic Editor so they may choose the right simulator platform, solver form factor and bitstream for the model to work as expected.

The below example uses an OP4510 with an eHSx64 form factor.

Similarly, even in HYPERSIM the I/O configuration needs to be made to ensure proper exchange of information between the FPGA and CPU solvers.

The figure below shows generation of the complementary PWM pulses through the OPAL-RT Board digital out subsection for the two-level converter built in the FPGA-based schematic circuit editor.

In this model the dead time is configured to 1micro-sec between the complimentary pulses

To configure PWM outputs, the modulation signals and the carrier wave frequencies need to be routed to the duty and frequency of the PWM output.

Simulation and Results

Open ScopeView to visualize the results. The graphs described below are provided in a template.

Initially the simulation starts in a null mode where all the inputs and outputs are 0.

At 0.5 s the DC voltage is provided to the two-level converter followed by enabling the controller to control the machine speed to spin at 1000 rpm and 50N-m Torque.

The motor reference speed and mechanical torque are added over time to understand the transient response and observe the speed control performance.

The results are shown in the figure below. The sequence of the mode change is shown in the table below.

Operating points	From	To	Speed Ref (RPM)	Load Torque (N-m)
1	0 s	0.75 s	1000	50
2	0.75 s	1.25 s	2500	50
3	1.25 s	1.85 s	2500	150
4	2.00 s	2.50 s	1000	50

The first page of the results are the machine three phase currents, set speed and measured speed, load torque and electromagnetic torque, and the mechanical angle of the machine.

In the second page, the motor's two phase d-q axis currents, power and reactive power are presented here for the operating range defined in the table. The machine is seen to track the reference speed even during the changing load torque conditions.

References

[1] Ming-Hung Chen and Hao-Ting Tseng, Development of Digital control for high power Permanent - magnet Synchronous motor drive, Hindawi Publishing Corporation Mathematical Problems in Engineering volume, June 2014

[2] Krishna Kumari N., Ravi Kumar D. (2018) Torque Ripple Minimization of a FOC-Fed PMSM with MRAS Using Popov’s Hyper-Stability Criterion. In: Bhuvaneswari M., Saxena J. (eds) Intelligent and Efficient Electrical Systems. Lecture Notes in Electrical Engineering, vol 446. Springer, Singapore

HYPERSIM Documentation

Examples | FPGA-Based PMSM Drive