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HYPERSIM Release Notes: 2020.1



  • Added new machine library models:
    • Synchronous machine (pu fundamental)
    • Synchronous machine (pu standard)
    • PMSM
  • Added new protection library model 25 Synchronism-Check
  • Added new machine control library model PSS4B
  • Added new Control Measurements and Control Miscellaneous components:
    • Fourier analysis
    • Fundamental
    • Mean
    • Mean, variable frequency
    • PI with anti-windup
    • Pos-seq, variable frequency
    • Power, 1-ph
    • Power, 3-ph
    • Power, instantaneous
    • Power, pos-seq
    • Power, pos-seq variable frequency
    • Sequence analyzer
  • Added new example models
    • Protection | Out of Step Detection using PMUs
    • Protection | Transformer differential
  • Added global preferences to specify the default system unit (SI/PU/PQ/A) per component type
  • Added various advanced preferences in the simulation settings
  • Added TrigOut observable to POW component and a mask parameter to define the pulse duration
  • Added handles in the UCM structure to manage solver iterations
  • Added support for relative paths for files defined in the I/O configuration tool
  • Added validation step when closing the UCM builder to warn the user of unsaved changes
  • Added Delete function in TestView


  • Improved display of parameters in mask of RLC, sources and tools when switching between 1-phase and 3-phase connection
  • Improved Sensor window view


  • Fixed display issues when the Windows preference for size of text and apps is not set to 100%
  • Fixed unresponsive I/O configuration tool when host IP address changes
  • Fixed various stability issues when host PC is connected to a VPN
  • Fixed non-persisting frequency parameter value in the load flow window when closing a design
  • Fixed synchronization of "Perform load flow and set initial conditions at simulation start" box between load flow and simulation settings views
  • Fixed Simulink import file browser filter indicating wrong supported version range
  • Fixed base voltages of Benchmark example models HVAC_6Bus_230kV and HVAC_38Bus_735kV
  • Fixed sensor file automatic load in DNP3_MASTER_SLAVE example model
  • Fixed topology category in the netlist for Voltage Source Converters
  • Fixed issue with the auto-transformer in the load flow calculations

I/O Interfaces


  • Added support for configuration via GUI

C37.118 Master

  • Added option to configure local UDP port

IEC 61850

  • Fixed scenario when the SVID has more than 126 bytes and/or when there are more than 16 channels configured per ASDU
  • Fixed import of projects created on a different host PC
  • Fixed IED and GOOSE ID auto-filling based on the SCL file


  • Added support for time-averaged digital inputs
  • Added support for PWM-synchronized analog inputs
  • Added support for .opbin bitstream configuration file extension
  • Improved browsing of .opal/.bin/.opbin files
  • Fixed random voltage output on unused analog output channels
  • Fixed disregarded 'Initial phase' value when 'Output complementary' is checked on digital outputs

FPGA-Based Simulation

  • Added example model Transportation | FPGA-Based PMSM Drive

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