Documentation Home Page HYPERSIM Home Page
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

HYPERSIM Release Notes: 2023.1




  • Improved Renewable Energy example model with native components instead of UCM for controls: 
  • Improved FPGA Scope workflow by adding a target network configuration in the Target Manager, see Quick Start | FPGA Scope for more information
  • Improved User Manual accessibility by adding a dropdown to choose what documentation to open between HYPERSIM, Dashboards, and Schematic Editor
  • Improved error message when starting the simulation and the hy.core process is down
  • Improved license request process


  • Fixed UCM dropdown menu not disappearing when clicking on Import UCM

  • Fixed code generation error when generated files path are too long
  • Fixed memory leak when repeating analysis on a model which increased the RAM consumption of HyWorks
  • Fixed auto-transceiver validation when several components within the same task are connected to its output
  • Fixed PQ Load component category in the netlist view
  • Fixed HyWorks Not Responding issue when inserting a wrong expression in the form
  • Fixed engine crash when modifying a 3-ph parameter in the netlist
  • Fixed equation consistency in Upward Ramp mask 
  • Fixed empty diagnostic page when installing HYPERSIM 
  • Fixed the following Python API commands:
    • setSignalLineColor
    • setSignalLineWidth 
  • Fixed Target I/O Interface component flipping after Analysis or Task Mapping if it has been flipped before
  • Fixed "Cannot Copy 'URP' is Null" when copy-pasting an integer value in the netlist
  • Fixed mapping between Target I/O Interface and 3-level NPC converter (SwD) components
  • Fixed Content Editor not setting value as an expression when no mathematical formula is involved
  • Fixed HYPERSIM crash when writing a wrong expression for a parameter


  • Removed RMI technology used by HyCore and other services. HYPERSIM 2023.1 will not be able to communicate with targets using version 2021.2 or older. If the latest installed version is 2021.2 or older, installing 2023.1 or a more recent version will require to first install any version between 2021.3 and 2022.2 as an intermediate version
  • Removed Python 2 API. Please consult the Python API | Setup page for migration information

I/O Interfaces


  • Improved NIC field to make it case-insensitive

C37.118 Slave

  • Added the possibility to apply an offset on the timestamp received
  • Added an error message when the Ethernet interface does not exist


  • Fixed “duplicate” option behavior

IEC 60870-5-104 slave

  • Fixed issue when more than 100 slaves are defined

IEC 61850

  • Added support for attributes with CO functional constraint
  • Added message to alert users that IEC 61850 Legacy interface will be removed in 2024.1
  • Added capability to timestamp MMS data with information from Oregano synchronization board
  • Improved MMS server configuration workflow by creating only the attributes defined in the SCL file
  • Improved parser to respect the structure data attributes order as defined in the SCL file
  • Fixed SV LE connections not being made when the network interface name has been edited
  • Fixed Sampled Values ID used in the packets sent by the simulator


  • Added support of INT32, UINT32 and INT16 for both master and slave


  • Added support for the following PWMOUT features
    • Allow disabling channel
    • Dynamic phase shift and dead time
    • Extended frequency range
  • Added capability to maintain common configuration elements when switching between bitstream configurations when Bitstream Configuration location is in the standard repositories
  • Improved displayed messages to avoid remote bitstream reprogramming failure
  • Fixed bitstream standard repositories not being refreshed automatically when changing the chassis type
  • Fixed issue in FPGA scope when the signal chosen as trigger is not selected
  • Fixed process cleaning in FPGA scope when the simulation is reset
  • Fixed Data Logger connection issue with the FPGA scope

Signal Generator

  • Fixed Square waves drift in time based on time step
  • Removed default CSV file and OPREC file when adding a signal generator


  • Added the possibility to apply an offset on the timestamp received from the Oregano board

  • Improved error message when checking for board/platform compatibility

  • Fixed Oregano example model fails when loading on Red Hat


  • Added IP aliasing capability
  • Fixed communication issue between HYPERSIM and LabView in Windows

Communication Network Simulation

  • Fixed freeze when seeing a wrong network interface in EXata CPS
  • Fixed mislabeled configurator

FPGA-Based Simulation

  • Added support for configuring scenarios from the CPU, allowing the definition of a very large number of scenarios, each being applied in multiple CPU time steps
  • Added support of Surge Arrester component in eHS Gen5
  • Added support of chassis OP4512 and OP4610 with new firmware
  • Added documentation for solver settings
  • Added a progress bar when the eHS circuit analysis is long (e.g. with many scenarios)
  • Improved user experience by not analyzing the eHS circuit if no changes were done
  • Fixed HYPERSIM starting simulation error without opening eHS component
  • Fixed DI signal reverse issue for eHS Gen5 on Kintex-7 410T FPGA
  • Fixed issue with single switches in Gen4 always using default values for Ron and Roff
  • Removed internal source as set parameter

A more detailed list of release notes is available at C:\OPAL-RT\eFPGASIM\v2.12.3.86\Docs\ReleaseNotes\Releases_Notes.pdf

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | | +1 514-935-2323