Block

Mask

Description

This is a block specifically designed for specific needs. It manages the changes made to device registers through the SPI link. It also manages automatic responses to Data Read/Write commands.

This is for the exclusive purpose of simulating a specific. The FPGA module emulates that behavior of the device with respect to spi commands. So, when a data Read command is received, the FPGA prepares the appropriate response.

The read values are determined from a set of registers containing values for:

8-bit current limit
8-bit test current limit
13-bit steering position
8-bit status flags

These registers may either be set by a data write command received through the SPI link or by the model using the block inports.

When a data write command is received, the data is simply set in the appropriate register.

Parameters

Controller Name: Name of the SPI controller to be used.

Inputs

Current limit	Current limit value to be placed in the FPGA. Applied only if the following Set signal is active.
Set	A value higher than 0.5 specifies to apply the Current limit value.
Test current limit	Test current limit value to be placed in the FPGA. Applied only if the following Set signal is active.
Set:	A value higher than 0.5 specifies to apply the Test current limit value.
Steering position	Steering position to be placed in the FPGA. Applied only if the following Set signal is active.
Set	A value higher than 0.5 specifies to apply the Steering position value. Applied only if the following Set signal is active.
Status flags	A 8 signals wide input where the signals specify status flags bits. Applied only if the following Set signal is active. The bits are defined as follows: Signal 1: ASIC over temperature Signal 2: VIGN indicates IGN turned OFF Signal 3: ECU_HOLD line is low Signal 4: DATA_HOLD lin is low Signal 5: MOSFET bridge is enabled Signal 6: Load dump bridge clamping in effect Signal 7: Hall effect counter error indicated Signal 8: ASIC uses normal current limit
Set	A value higher than 0.5 specifies to apply the Status flag value.

Outputs

Current limit read	Returns the current limit value present in the FPGA.
Test current limit read	Returns the test current limit value present in the FPGA.
Absolute Steering Position Counter	Return the absolute steering position counter value present in the FPGA.
Internal Status	Returns the Internal Status of the board. It is an 8 signals wide output that carries the same definition as the Internal Status input. Signal 1: ASIC over temperature Signal 2: VIGN indicates IGN turned OFF Signal 3: ECU_HOLD line is low Signal 4: DATA_HOLD lin is low Signal 5: MOSFET bridge is enabled Signal 6: Load dump bridge clamping in effect Signal 7: Hall effect counter error indicated Signal 8: ASIC uses normal current limit
Modes read	Returns the mode selection bits currently set in the FPGA. It is a 6 signals wide port where each value is defined as: Signal 1: Hall effect strobed mode select bit Signal 2: Mode select bit Signal 3: Hall effect invalid count latch clear request bit Signal 4: Position counter reset request bit Signal 5: Reset ECU hold request bit Signal 6: ASIC RAM reset request bit

Characteristics and Limitations

Direct Feedthrough	No
Discrete sample time	No
XHP support	Yes
Work offline	No

RT-LAB Documentation