To use OPAL-RT I/O modules, an OpCtrl block is required in the RT-LAB model.
This block controls the programming of one OPAL-RT FPGA, its initialization and the selection of the hardware synchronization mode of the card.
It also enables binding of Send/Recv and I/O blocks to that specific card.
The OpCtrl block can be found in the Simulink block library path: RT-LAB I/O > Opal-RT > Common > OpCtrl
In the Integration Test Model provided, the block parameters for the OpCtrl block are already set as follows.
This information is provided for reference, mostly for advanced users. Most users will want to use it “as is”.
OPAL-RT controller parameters | |
Parameter | Value |
Controller Name | 'OP4610XG OpCtrl' |
Board ID | 0 |
Primary Bitstream FileName | TE0741_4-EX-0001-3_4_1_816-eHSx128m_Gen4_DBDBD8C322QEIO-4F-34.bin |
Synchronization mode | Master |
Generate External Clock | ☐ (Unchecked) |
Sample Time (s) | 0 |
Board Type | TE0741 |
Synchronization type | Optical fiber (strongly recommended) / Audio |
Disable strict hardware mismatch validation | ☐ (Unchecked) |
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