Description

This block implements a signal mapping and rescaling interface to control analog output channels according to signals originating from the RT-XSG (FPGA) or RT-LAB (CPU) model. The signal mapping as well as the gain, offset, min and max are configured from the RT-LAB model or the Schematic Editor.

This block is capable to map from up to eight serial input in

the OPAL-RT FLWS Protocol

 format to 32 analog output channels.

Inputs

Sync:

 This input must be a Bool or UFix1_0 signal. It should be a pulse train whose period is equal to the sample time requested for the Analog Output channels. Refer to the Hardware documentation for the minimum sampling time of the interface.

DataIn:

 This input should be connected to the solver's Data In configuration port.

DataInSof:

 This input should be connected to the solver's Data In configuration start of frame port.

LoadIn:

 This input should be connected to the solver's Load In configuration port.

LoadInSof:

 This input should be connected to the solver's Load In configuration start of frame port.

Model Signal Serial {1..8}:

 These inputs are providing the FPGA signals that could be mapped to the analog output channels. They have to follow the OPAL-RT FLWS Protocol. Inner data size is 32 bits (i.e XFloat8_24), any additional bit would be discarded. Each input can transport a maximum of 128 channels. As an example, this signal could be provided by eHS solver. (Gen4

 onwards).

Outputs

Configured SLOT_1:

This output returns the state of the

first slot selected in the block dialog (in the above image, 1A), whether it is configured or not. If this slot is configured by receiving Data on its Load In signal that is to be sent to the first slot, the Configured port outputs 1. If not, the Configured port outputs 0. Note that this output does not appear if the first slot is set to "unconnected."

Configured SLOT_2: This output returns the state of the second slot selected in the block dialog (in the above image, 3B), whether it is configured or not. If this slot is configured by receiving Data on

its Load In signal that is to be sent to the second slot, the Configured port outputs 1. If not, the Configured port outputs 0. Note that this output does not appear if the second slot is set to "unconnected."

Out: This bus output contains the following signals

• Conv1:

•  This output is conversion command that should be connected to the first Analog Output I/O interface.

• ch{0..15}:

•  These outputs are the 16 mapped and rescaled channels that should be connected to the first Analog Output I/O interface. The output format is Fix16_11.

• Conv2:

•  This output is conversion command that should be connected to the second Analog Output I/O interface.

• ch{16..31}:

•  These outputs are the 16 mapped and rescaled channels that should be connected to the second Analog Output I/O interface. The output format is Fix16_11.

Characteristics and limitations

The use of this block is limited to analog output interfaces that accept the Fix16_11 fixed-point format for their inputs. And be aware AOMR block ID is no longer used in this block.

If you require more information, please

contact https://www.opal-rt.com/contact-technical-support/.