Description

This block allows the configuration and the control of a eHS Gen3 solver to compute the outputs of a power-electronic circuit. The eHS Gen3 core is located on an FPGA-based board and runs at a higher sample rate than an RT-LAB system. The netlist file can either be a SimPowerSystem a Simscape Electrical Specialized Power Systems (SPS) Simulink  Simulink model, a PLECS Simulink model (.mdl), a PSIM netlist (.psimsch), or an NI Multisim netlist (.xml).

The block enables the real-time control of its voltage and current sources, as well as the gate signals of the switches. In addition, it supports scenario management.

Mask Parameters

Circuit Tab

eHS Solver form factor: This option selects the solver computational unit form factor. It must correspond to the solver form factor in the firmware. This information can be found in the firmware documentation.

Circuit file name: Links this block to a file describing the circuit intended to be simulated using eHS. The system should be built using the SimPowerSystem SPS Toolbox. See the product documentation and example models for details on how to design the circuit for use with the eHS.

Provide explicit sample time for solver eHS: If this option is selected, the Sample time for eHS field is made available to set the solver sample time. The minimal solver sample time depends on the complexity of the circuit, and typically ranges in the hundreds of nanoseconds.

This may be helpful for:

• Accelerating the offline simulation. For offline simulation, the step size has to be set to the greatest common divisor of the eHS step size and the real-time (RT-LAB) system step size (down to 5 ns without setting an explicit sample time).
• Testing different sample times
• Reducing the quantization error for systems that contain very large time constants (>> 10sec)
• Synchronizing the eHS with another FPGA solver core

Show advanced settings for eHS solver: This checkbox allows the user to modify the switch conductance and initial voltage and current values. If unchecked, the last applied configuration of these parameters will be used.

Gs: This parameter is the conductance of the switches of the circuit. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved. Valid values of Gs are positive or null. However, while null values are allowed, they may lead to incorrect simulation results and using them will trigger a warning display.

To open the eHS Optimization Tool in order to get more info on this parameter, type GsGui2 into the MATLAB Command Window.

Infos Tab

This tab gathers information related to the last valid loaded netlist.

This information includes the netlist name, the minimum achievable time step, the number and enumeration of inputs (sources), the number and enumeration of outputs (measurements), the number and enumeration of switches, and the number of states to be computed.

It is especially helpful to identify the order of the sources, measurements, and switches from the netlist file using the information in this tab. The naming order is alphabetical for Sources, Measurements, and Switches, and includes the subsystem name, if applicable, of each element.

If the netlist file is not read correctly and the input, output, and gates assignation is incorrect, the results of the simulation will not be valid.

Inputs Settings Tab

Voltage/current controlled sources provided: This parameter enables the developer to choose whether the simulated circuit inputs should be controlled from this blocks inputs (i.e. Constant from RT-LAB or FPGA Sine Wave Generator controlled by RT-Lab block) or from an internal FPGA signal (i.e. Analog inputs). For the latter, the internal FPGA signals must be provided to the eHS core in the simulation platform firmware. Please refer to the firmware documentation for the availability and definition of such signals. The sources control can be set independently using the Independent Setting for each element option. For all settings except the latter, the index of the control signals is equal to the index of the element as defined in the Input Enumeration of the Infos Tab.

Voltage/current source control enumeration: This setting is available only when the previous parameter is set to Independent Setting for each element only. It allows the user to route the inputs' sources independently for each input element. It should be a [U x 2] matrix, where U is the number of sources in the circuit to simulate, in which the first line corresponds to the source configuration of the first Source, the second line to the one of the second Source, etc. Please refer to the Input enumeration field in the Infos Tab to identify the index of each input. The first element of each line reports the source type as described below and the second element reports the signal index within this source type. The source types are as follows:

• 0: the corresponding input will be driven by the RT-LAB input port (this block's INPUTS input).
• 1: the corresponding input will be driven by an analog input. If any source is set to be controlled from an analog input, the Analog Input Differential Rescaling block should be present in the model and configured appropriately.
• 2: the corresponding input will be driven by another eHS core. If any source is set to be controlled from another eHS core, another eHSx64 Gen3 CommBlk should be present in the model and configured appropriately.
• 3: the corresponding input will be driven by the embedded sine wave generator.

Use as many inputs as the current netlist requires: When enabled, this option will perform a netlist analysis to determine how many inputs are required and will set the Number of inputs used parameter accordingly.

Number of inputs used: This parameters sets the number of inputs that will be sent to the FPGA core. In order to limit the communication overhead and enhance the real time performance, it is advised to use as few inputs as possible.

Note: The size of the signal driving the block INPUTS and sine wave generator ports must comply with the number of inputs specified in the circuit model. The Use as many inputs as the current netlist requires setting and the Number of inputs used are two ways that allow the user to scale the number of inputs enabled.
For example, if 16 inputs are enabled, only a vector of 16 values can be connected to the INPUTS port. Also, 16 inputs for frequency, amplitude, and phase must be provided to the Sine Wave Generator ports.

Use embedded Sine Wave Generators: The eHSx64 Gen3 package contains a 32-channel Sine Wave Generator embedded inside the FPGA. It can be used to replace the standard inputs from RT-LAB.
The sine wave generator has a fine resolution (down to 140ns) which is much more performant than a typical RT-LAB model time step (10-100us).
Three input ports will be added to the RT-LAB block in order to drive the frequency, amplitude, and phase of each sine wave generator channel.

Note: If the user enables this option, Frequency, Amplitude, and Phase inputs will be added to the block. The user must provide these inputs with vectors whose size match the number of inputs that have been enabled. To synchronize multiple sinewaves, it is important to always provide the same frequency values to these inputs.

Sine Wave Generators LoadIn port number: When the sine wave generators are enabled, the user must provide the LoadIn port number to communicate with the generators. With the standard firmware provided with eFPGASIM, the default port number is 3.

Gates Settings tab

Switch source control: This parameter enables the developer to choose whether the simulated circuit switches should be controlled from this block's inputs (i.e. from RT-LAB) or from an internal FPGA signal. When using the latter, the internal FPGA signal must be provided to the eHS core in the simulation platform firmware. Please refer to this firmware documentation for the availability and definition of such signal.

Gate Control Selection Panel: This button is available only if the Switch source control parameter requires the control to be selected on a switch per switch basis. It enables the user to choose the gate control source, channel index, and its polarity for each switch found in the circuit.

Note: This parameter must be a 72-element vector even if not all of the 72 switches are used.

Number of gates from RT-Lab: The number of gated signals, controlled by this block (i.e. from RT-LAB), that are enabled. The gate number will be shared by the RTE gates and static gates.

RTE Gates: Gates range that will be controlled by the Gates RTE input port of this block.

An RTE signal allows for the creation of digital signal that will perform transitions during a CPU time step at specified times.

A static digital signal, in contrast, is sampled at the beginning of next CPU time step and is latched for the duration of this time step.

If SW01-00 is selected, the Gates RTE input port will be removed.

If less than the total number of gates is selected, a Gates Static input port will be added. The gates that are not in the range defined by this parameter will be controlled by the Gates Static input port.
Otherwise, the Gates Static input port will be removed from the block, all the gates activated will be accessible by the Gates RTE input port.

The none setting used to indicate that no Gates RTE are present is replaced by the SW01-00 setting. None is still present to ensure retro-compatibility with previous versions of the block. However, this setting will automatically be reverted to SW01-00 and a warning message will be issued. None will be removed in the future.

Maximum number of events for pulse control: This parameter sets the maximum number of transitions per calculation step on the switches. Its value needs to be at least equal to the maximum expected count of all transitions on any single gate input of the solver during one time step. This parameter is applied to all RTE digital signal generators.

Static Gates: This parameter provides information about the gates that will be driven by this block's Gates Static input port.

Switch polarity: This parameter enables the developer do choose whether the simulated circuit switches should be active-high or active-low.

Switch polarity enumeration: This parameter is available only if the Switch polarity parameter requires the polarity to be selected on a switch per switch basis. It should either be a scalar (applied to all switches in the circuit) or a vector enumerating the polarity, with indices 1 to 72 referring to SW01 to SW72 in the simulated circuit. For each element, the value determines whether the switches should be active-high (indicated as a 0) or active-low (indicated as a 1).

Scenario Management Tab

The scenario feature allows the user to define multiple sets of values for the netlist RLC components. For each scenario, the user will be able to modify the values of the components.

Enable scenarios: By checking this option, the scenario feature will be enabled.

XLS File name: The XLS file contains the table of RLC components values depending on the scenario number. This parameter gives the path of the file that will be used to perform the scenario declaration.

Command: Option "Create a XLS template for the current netlist": this option will create a template file at the name and location set in the XLS File name GUI input.
The Update eHS configuration file with current scenarios option will update the eHS configuration MAT file with the scenarios declared in the current disk version of the XLS file.

XLS active sheet number: The scenario feature supports multiple sheets in the XLS file as long as each sheet format conforms to the Make a Scenario XLS file tutorial. The sheet number must be a positive non-null integer. The sheet must exist for the reading operation to succeed.

Maximum number of scenarios available with current netlist: This represents the number of scenarios available for the current netlist. This number takes into account the scenario of default values that cannot be modified.

Comm Settings Tab

Controller name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Sample Time: This parameter should be equal to the sample time of the real-time subsystem in which the block is located.

Set Communication Port Numbers (Advanced Users): This parameter is enabled by default and allows the user to set the CommunicationPortNumbers parameter.

CommunicationPortNumbers: This parameter should reflect the 13-element series of communication ports used to communicate data between the real-time model and the hardware solver via the PCIe link.

• Element 1= LoadIn port number for eHS configuration
• Element 2= LoadIn port number for eHS reset
• Element 3= DataIn in port number for eHS inputs from CPU
• Element 4 to (N-1): DataIn port numbers for eHS TSDO generators (RTE gates)
• Element N: DataOut port number for eHS outputs to CPU

Note: For eHSx64 and eHSx128, this block expects 13 communication ports (N=13). For eHSx32, this block expects 10 communication ports (N=10). This information is found in the documentation of the I/O interfaces of the simulation system or in the RT-XSG source model of the bitstream, and is system specific.
Default values are [1 2 1 2 3 4 5 6 7 8 9 10 1], for eHSx64 or eHSx128, and [1 2 1 2 3 4 5 6 7 1] for eHSx32.

Inputs

INPUTS: This input should be a vector, each element being one of the controlled inputs of the eHS solver. The width of the vector should correspond to the Number of inputs used parameter of this block's mask. Indices that do not correspond to a controlled voltage or current source are left unused. Please refer to the Input enumeration field in the Infos Tab to identify the order of the inputs.

SinWaveGen Freqs|Amplitudes|Phases: This input should be a vector, each element being one of the frequency/amplitude/phase of a Sine Wave Generator. The width of the vector should correspond to the Number of inputs used parameter of this block's mask. Indices that do not correspond to a controlled voltage or current source are left unused.

GATES RTE: This input should be a vector, each element being one of the switch gates of the eHS solver. The width of the vector should correspond to the size of the range assigned in the RTE Gates parameter of this block's mask. The format of each gate signal should be of RTE type, with the number of events defined in the block's mask.

GATES STATIC: This input should be a vector, each element being one of the switch gates of the eHS solver. The width of the vector should correspond to the size of the range displayed in the Static Gates parameter of this block's mask. The format of each gate signal should be of Double data type.

SCENARIO_ID: This input should be a scalar defining the scenario that the solver uses. When changing scenario, the set of component values used will be the one specified in the XLS file at the corresponding scenario lines. The default configuration is 0. The inputs values to load Scenarios1..N are 1..N. The input is not overflow protected, thus if the maximum number of scenarios is 32, sending 34 to the input will load scenario3.

Reset: This input is a software reset. When set to 1, the solver is in reset mode. When set to 0, the solver is not in the reset mode.

Outputs

OUTPUTS: This output is a vector, each element being one of the outputs of the solver. The width of the vector is equal to the number of measurements in the block. Note that the outputs of the eHS Gen3 block are the average values of the FPGA solver output over a CPU time step.

Status: This output is a vector, each element being one of the LoadIn/DataIn/DataOut communication port statuses. The first element corresponds to the Reset LoadIn port status, the second element to the eHS configuration LoadIn port status, the third to the input DataIn port status and the fourth to the output DataOut port status. In normal operation mode, they should all be 0s, except the Reset LoadIn port status which should be -1. Refer to the LoadIn, DataIn Send and DataOut Recv blocks help file for details about the status codes made available from this port.

Writing an XLS Scenario File

Getting Started: The easiest way to write the first XLS file is to generate a template. To do so, the user can select the command Create a XLS template for the current netlist from the Scenario Management tab or manually create the table. The first line, from B1 box, is reserved for RLC components declaration. The first column, from A2 box, is reserved for the scenarios declaration.

Filling the component line: The first line of the table, as of cell B1, is reserved for the component declaration. The component name is the netlist name from the top-level of the netlist (e.g. subsystem/componentname). If the component is inside a branch, its name will be the branch name with the suffixe .R, .L or .C, depending on the type of the targeted component.

Filling the scenario column: The first column of the table, as of cell A2, is the scenario declaration. Scenario labels must respect the naming convention Scenario followed by the scenario number. For example, the scenario number 21 right label will be Scenario21.

Default scenario line: The Default label is reserved to display the default values of each component. This is used for information only and not as actual netlist default values. Instead, the netlist file components values are used as default.

Removing lines/column: Removing lines (scenarios) and column (components) from the table is allowed. As a result, the removed scenarios and components will be kept at default values.

Filling the table: For each scenario, define the component parameters that need to be modified. Enter these scenario's component values in the table. Leaving an empty box will leave the component's value unchanged by the scenario. Thus it will keep its default value.

Number of modifications allowed by scenario: For each scenario, all declared components allow for their value to be modified. There is no limitation on the number of components that can be changed by a scenario.

Non-existing component: If a component is declared in the XLS table, but does not exist inside the netlist (wrong label/component removed), this column will be ignored, and will not have any effect on the scenario generation.

Non-existing scenario declaration: If a scenario is impossible (wrong label or scenario number greater than the maximum number of scenario feasible), an error will be thrown.

Verifying that the scenarios are well generated: While generating an eHS Gen3 configuration, a log is generated in MATLAB Command Window detailing the effective changes made to the netlist depending on the scenario number.

Characteristics and limitations

Number of elements: The limitation on the number of elements (i.e. Sources, Gates, and Measurements) depends on the eHS form factor being used. For updated information on the limitations of each eHS Gen3 form factor, refer to the Specifications section of the User Guide.

• There is no limitation on the number of resistors.
• The solver time step is limited to approximately 2.56us.
• As many inductors and capacitors as necessary can be used so long as the timestep does not surpass the limit of approximately 2.46us.
• The use of Inductors, Capacitors and Switches has a strong impact on the minimum achievable timestep, whereas the use of inputs and outputs has a more limited impact.

Circuit design: See the product documentation and example models for details on how to design a circuit for use with the eHS.

Offline simulation: This block does not enable offline simulation. For offline simulation, use the eHS Offline simulation block in the eFPGASIM>>eHS and Converter Models>>Tools library. This block enables the developer to connect the block exactly as it is connected inside the FPGA, e.g. to a plant model, for more accurate results.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.