Description
This component allows creating, editing, configuring and running an FPGA-based circuit. It provides access to a schematic editor specifically designed to develop models for FPGA-based simulation. All models developed with this interface are available to all projects through a shared databaseThe model is an ehs3 file which is loaded into the component. Various parameter sets can also be predefined to enable switching test cases while the simulation is running.
For more information on how to use the schematic editor, see OPAL-RT Schematic Editor Documentation
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Mask and Parameters
Starting 2024.4, this component does not rely on a Mask. It is configured by context menus on the schematic (Ctrl + Right Click).
Open in Schematic Editor: Equivalent to double clicking the component on the circuit, it opens the currently selected circuit in Schematic Editor. If no circuit is currently assign, a choice between creating a new circuit or selecting an existing one will be presented.
New Circuit: Creates a new ehs3 file where requested on the file system, assigns it to the component and opens it instantly in Schematic Editor.
Edit: Selects an ehs3 file on the file system, assigns it to the component and performs a loading of the circuit.
Load circuit: Load the selected circuit in the HYPERSIM model and automatically redraw the block and generate the I/O and FPGA configurations.
Open build report: Opens the report of the last "Load Circuit" operation.
Show in explorer: Opens an explorer to the folder containing the ehs3 file associated to this component.
Open Documentation: Opens the local documentation of this component
Recommendation : For portability, it is recommended to keep this ehs3 file next to the ecf file of this model. The Project Import-Export menu will automatically select this file as part of the export.
Ports, Inputs, Outputs and Signals Available for Monitoring
The inputs and outputs of this model are generated dynamically depending on the sources, switches and measurements present in the FPGA-based model.
Additionally to these inputs/outputs a parameter_set_id pin allows controlling the parameter set selection from the CPU model.
Ports
Network connections are not supported at the moment.
Inputs
Controlled sources inputs: drive the controlled current and controlled voltage sources from the FPGA-based model
Switches inputs: control the switches from the FPGA-based model
parameter_set_id: Parameter set ID. Only used by the component if the parameter set source is set to "External"
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if parameter_set_id value is not valid, the previous valid value will be used |
Outputs
All outputs represent measurement components placed in the FPGA-based circuit
Sensors
All input and output pins are also available as sensors for monitoring in ScopeView.
Parameter Sets
Parameter sets allow changing multiple FPGA-based circuit's component parameters during the simulation, without having to re-flash the firmware or stop and restart the simulation. Parameter set values, names and ID can be defined from the schematic editor while editing the FPGA-based circuit.
If any parameter set is present in the circuit, the parameter_set_id pin will be added as part of the input pins of the component.
Multi-eHS
From 2025.1, support for multiple eHS models in the same HYPERSIM circuit has been introduced.
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Under the _hyp folder next to the ecf, under configurationsIO/OpalBoardsAddons, internal data is kept to map the connections between the HYPERSIM sensors and the eHS datapoints. In order to support multiple eHS models, the file structure changed in 2025.1, so that each component is given a specific subfolder. Therefore, a model made in 2025.1 will not be supported in 2024.4 |
During the simulation startup, HYPERSIM will need to connect each OPAL-RT Board with the correct eHS model. To do so, it will rely on 2 information which need to be consistent :
The chassisId mentioned both in the OPAL-RT Board and in the Schematic Editor, in the Simulator Setup section
The bitstream type mentioned both in the OPAL-RT Board and in the Schematic Editor, in the firmware selection menu
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In the case of a single eHS model simulation, the chassisId in the Schematic Editor may be left to automatic. If only 1 OPAL-RT Board and 1 eHS model are present and have consistent bitstream, then it will be assumed that they work together. This ensures the migration of models from 2024.4 and lower to 2025.1. |
Troubleshooting
When clicking Load circuit, the configuration files are automatically generated in the model _hyp folder. Thus, to properly share a model using an FPGA-based circuit component, one has to copy the _hyp along with the .ecf file.
In the case where loading a circuit fails, a notification message appears.
Opening the report will provide additional details.