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OPAL-RT Board


Description

The OPAL-RT board I/O interface allows the user to configure the various OPAL-RT analog and digital I/O boards.

To access the user interface, click the I/O Interface Configuration button in the HYPERSIM ribbon options

In the window that appears, right-click OPAL-RT Board and select Add.

After giving a relevant name to the I/O interface, its user interface is available for use.

The I/O interface must be configured, and valid connections must be defined before the I/O interface can be initialized at simulation start.

One  I/O interface per FPGA must be used. To differentiate one from another, they must have unique names.

Bitstream Configuration


Every bitstream file (.bin) or programmable definition file (.pdi), programmed into an FPGA interfaced with the OPAL-RT Board driver must have an associated configuration file. The driver requires a description of the hardware installed in the simulator to correctly interface with it. Via the standard Opal-RT repositories option, Opal-RT Board allows the users to navigate through the bitstream configuration files available in the installed version of eFPGASIM and RT-LAB. Alternately, the user can browse to a bitstream configuration file using the Windows File Explorer with the file system option.


 


Note that DOV (Default Output Value) is present in bitstreams created with RT-XSG v3.2.6 or later. See also RT-XSG

This feature makes it possible to have control over the behavior of the output signals during PAUSE or RESET states. Values and behaviors are chosen before generating the bitstream and are not user-modifiable afterward.


 

A bitstream configuration file describes all the functionalities of its associated programmable file.

The configuration contains information about the I/O communication and the presence and configurability of other logic blocks (such as electric solvers) in the RT-XSG model used to generate the programmable file.

To configure the OPAL-RT Board interface, a valid .opal or a valid .opbin file based on the board type must be selected by the Bitstream configuration file option. A .opbin file is a package that manages several files needed to configure and load an OPAL-RT Board simulation. A minimal .opbin file contains the information available in both a .opal file and a bitstream file.

As described above, these files can be selected with the Windows File Explorer or within the proposed files located in the standard Opal-RT repositories.

Before selecting a .opal file within the File Explorer, the user must ensure that the associated bitstream file (.bin) is in the same folder. (This issue is managed automatically when using a .opbin file or using the standard Opal-RT repositories.)

Before executing the model, the user must verify the Automatic bitstream reprogramming option.

  • With this option enabled, the bitstream is flashed automatically at each load of the model.

  • If the same bitstream is detected, then it is reloaded in the FPGA.

  • To bypass any programming/reload, the option must be disabled.

  • To force the programming regardless of the bitstream being the same, the Force checkbox must be enabled.

If the Automatic bitstream reprogramming option is not available, it means the bitstream file was not found.

To overcome this issue, follow these steps:

  • Make sure the .opal file given by the field Bitstream configuration file exists.

  •  

    • If it doesn't exist, find it and copy it in the project directory.

  • Copy the .bin file in the project directory.

  • Close the I/O Interface Configuration.

  • Re-open the I/O Interface Configuration.

The OPAL-RT Board interface shows the name of the expected bitstream file when the configuration file (.opal or .opbin) has been correctly imported.

 


Note:  When opening a project for the first time, the I/O Interface Configuration must be open to ensure that the Opal-RT Driver has correctly initialized his bitstream configuration file(s). This step is required if the user wants to use the Automatic bitstream reprogramming functionality.


 

For a list of the possible chassis and board/module combinations, consult the List of Compatibilities section.

See the General Configuration section below for more details on changing and loading bitstream configurations.

Configuring Remote I/Os

Loading the bitstream configuration lets users know if the MuSE (Multi-System Expansion link) feature is supported. This feature expands the I/O capability of the simulator by enabling the connection to multiple FPGA-based I/O expansion chassis or OP4200 systems. Thus, it allows the user to configure, connect to, and control I/Os belonging to a remote FPGA. The connection is made through high-speed optical fiber cables and SFP transceivers, using the SFP sockets available at the front or the left side of the chassis.

The user can verify if the MuSE feature is supported directly after loading a bitstream configuration file. If the feature is present, a list labeled Remote Board Configuration appears in the UI. From this point on, the system can be referred to as a central system. A central system is an FPGA whose bitstream gives it the capability of connecting to one or multiple remote FPGAs.

One remote chassis can be connected to each SFP socket of the central. The network of central and remote chassis is thus a star topology, with the central system in the center and the remotes as its endpoints.

The remote chassis status as endpoints means that they cannot be used as central systems (daisy-chaining of remotes is not supported), so a bitstream file prepared for a remote chassis cannot be used for a central system.

Hardware synchronization of the systems is achieved through the same high-speed link as the one used for data transfer (i.e. only one cable is required at all times between the central system and any of its remotes).

 


Unlike the PCIe expansion chassis, the order in which the systems are powered on, or the order in which the cables are connected, does not matter. Nor does it matter whether or not the systems are on while the cables are being connected.

What is important is that the system topology is set in place (i.e. all cables connected according to the simulation's requirements) before the start of the simulation and that it remains connected throughout the simulation.

Changes to the topology cannot be made while the simulation is running.


 

The programming of remote bitstreams is done by invoking the flashing application executed on the central system.

For more information on how to do this, please contact OPAL-RT's support team.

Please check the Remote Board Configuration section below for more information on how to set up remote systems.

Restrictions to using the Multi-System Expansion link with software architecture may apply depending on your application and software configuration.

To verify compatibility, please contact OPAL-RT's support team.

For a list of the possible chassis and board/module combinations, please consult the List of Module Compatibilities for the MuSE feature section.

Interface Overview: Configuration

The I/O interface is entirely configurable via the HYPERSIM interface. Parameters available for configuration are presented in this section.

General Configuration

The following options can be configured when clicking the I/O interface main configuration page:

Chassis type

Select the FPGA board type used in the simulation.

Chassis ID

Enter the chassis ID of the selected FPGA board used in the simulation.

Clock mode

A choice must be made between HW (hardware) or SW (software).

The choice of clock establishes if the FPGA drives the simulation (hardware mode) or the CPU (software mode) does.

Use external synchronization source

When selected, the board uses an external hardware synchronization source as opposed to its internal clock.

This option is not taken into account if the Clock mode is SW.

Type of generated synchronization signal

If the Use external synchronization source box above is unchecked, then this parameter is visible, allowing the user to choose the medium where the FPGA outputs its synchronization pulse: choices are through the optical cable or through the audio cable.

NOTES:

  1. This parameter is only relevant when the Clock mode is HW

  2. Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly.

Operate as hardware synchronization source

This checkbox is only visible if the Use external synchronization source checkbox above is enabled. Its purpose is the following:

  • When enabled, the FPGA is configured to use the external synchronization source received to synchronize the simulation (master-with-external-clock mode)

  • When disabled, the FPGA is configured to use the external synchronization source received, but it will not qualify to drive the simulation (slave mode)

NOTE: This parameter is only relevant when the Clock mode is HW.

Type of expected synchronization signal

This parameter is only visible if the Use external synchronization source checkbox above is enabled.

It is a drop-down menu giving the user the choice to synchronize either through copper or optical cables.

NOTES:

  1. This parameter is only relevant when the Clock mode is HW.

  2. Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly.

Bitstream configuration location

This field chooses between searching the bitstream configuration file using the file system, or by selecting it from a drop-down list based on the available files present in the standard OPAL-RT repositories.

Bitstream configuration file path

If the bitstream configuration location is set to File system
A file-browsing field appears.
Clicking it opens a File Explorer window to navigate to the bitstream configuration file.




If the bitstream configuration location is set to Standard repositories:
A drop-down with the available configuration files found in the standard OPAL-RT repositories appears.

Once a file is selected and the interface has checked validitythe Folders section of the configuration panel updates to show the I/O capability of each slot as described in the file.

Show advanced configuration

When selected, the options presented below are available to the user.

NOTE: these options require advanced knowledge of the I/O interface capabilities

Time step factor

Denotes a multiplier for the board's speed in relation to the model's timestep.

NOTE: Only visible when Show advanced configuration checkbox is enabled.

Enable FPGA register logger

For advanced debugging purposes, the driver will start a tool that will log all the FPGA register accesses during the initialization and the reset of the model. The logs will be saved in files named with the prefix "register_trace*".

NOTE: Only visible when Show advanced configuration checkbox is enabled.

Level of logging

Select how verbose the log should be. The higher the level, the more impact it may have on the simulation performance.

NOTE: Only visible when Show advanced configuration checkbox is enabled.

Enable the firmware generated update request signal

This feature is only available in SW synchronized mode and when data is sent at the beginning of the calculation step.

When enabled, it allows the firmware to generate the update request signal instead of letting the software application generate it.

NOTE: Only visible when Show advanced configuration checkbox is enabled.

Automatic bitstream reprogramming

If selected, bitstream programming is triggered automatically at the model load. The bitstreams should be placed at the model path and must have the name given in the configuration file used. If the bitstream currently programmed in the board is found to be the same as the one about to be programmed, then the bitstream is reloaded into the FPGA. This field is not available if the bitstream file is not found.

Bitstream file name

An uneditable field showing the bitstream found based on the selected bitstream configuration file.

Force

This option flashes the board even if it is already programmed with the same bitstream.

Disable strict hardware mismatch validation

If selected, the use of multiple I/O card types based on general compatibility rules is activated instead of exact hardware ID values.

Chassis name

This field will be available for the user to configure a custom name to be displayed on the Chassis LCD.

NOTE: Only visible when Chassis type is OP4810 or OP4815.

IP address

In order to allow bitstream programming, this field will be available for the user to enter the appropriate IP address that is displayed on the Chassis LCD.

NOTE: Only visible when Chassis type is OP4810 or OP4815.

Enable FPGA Scope

If selected, the FPGA Scope will be available when the model is executed. The option is visible only if the feature is available in the selected bitstream configuration file.

Enable virtual mode

In virtual mode, the model can be executed even if this I/O interface is not compatible with the hardware configuration of the system. The connections between the model and the I/O interface will be done during the initialization, but the I/O interface will not do anything. The virtual mode can be used to troubleshoot problems on a system without having the required hardware, or to prepare a model with different I/O interfaces even if the final hardware platform is not available.

Slot configuration

When this section is clocked, the fields provide the following information to the user:

Name

The name of the slot; describes the location in the simulator chassis and its functionality

Description

Electrical characteristics of the board defined in this slot

Functionality

I/O type and direction of the board defined in the slot

I/O card type

I/O board identifier. In the case of OP4200, this represents the cassette's identifier.

Other parameters may appear here, depending on the I/O board type.

Channel Group Configuration

A group contains eight channels, with the following configurable options:

Enable: Enables data transmission/reception of the specified channel group.

Other parameters may appear here, depending on the I/O board type.

Signal Configuration

This section allows the user to configure the characteristics (if any) of each of the 8 channels available in a group. The content of this panel varies based on the I/O board type defined in the slot.

For more information regarding the detailed configuration of the signals, refer to the corresponding I/O type documentation in the sections below:

Remote Board Configuration

Add remote systems to the configuration by clicking the Insert button in the Remote Board Configuration list. This list is only visible if the MuSE feature is available in the current bitstream configuration. 

The name of each remote can be changed in the remote list view of the interface.

Following this, the configuration of each remote (such as chassis type, chassis ID, bitstream configuration, and so on) is done by clicking the respective remote in the interface.

The view that appears is the same as the one for the central system. Users can refer to the beginning of the current section, starting with General Configuration for more information.

Similarly to central systems, bitstream configuration files describing bitstreams for central (or standard, non-MuSE) FPGAs cannot be loaded for remote systems.

When the remote system chosen is an OP4200, the user has to provide its MAC address. The MAC address can be found by running the "ifconfig" command on the remote system, or by consulting the delivery binder. The format expected is XX:XX:XX:XX:XX:XX, where X is a hexadecimal digit (0-9, A-F).

Currently, remote systems are forced to be synchronized slaves. This can be seen through the Use external synchronization source checkbox being selected but grayed out. Remote systems must be synchronized with the central system (i.e., they cannot use any other synchronization source). The physical synchronization between central and remote systems is done through the same optical cable used for the data transfer (i.e. only one cable is needed between a central and any remote).

Chassis Type Update

The scenarios below show the different possible options when changing the chassis type.

1. When changing the chassis type, a warning will be displayed to notify the user that the bitstream configuration file might need to be changed. Regardless of the user input, the existing configuration is maintained.

If the bitstream configuration file does not match the new chassis type, the configuration can not be saved. The user will have to update the bitstream configuration file to one that is compatible with the chassis type chosen.

2. A central board's configuration can be reset at any time by changing the chassis type to Select a valid chassis type.

Bitstream Configuration File Update

When the bitstream configuration file is changed (whether to re-upload the same file whose contents might have been modified or to change the file entirely), a change detection mechanism will help the user make an informed decision about whether or not to continue with the update.

Bitstream configuration file change workflow

The following steps explain the workflow:

1. Select a bitstream configuration file (the same or different) from the drop-down containing available configuration files when Bitstream configuration location equals to Standard repositories or by clicking on the browse button when Bitstream configuration location equals to File system. This will bring up the refresh menu, asking how to proceed with the configuration's editable parameters that originated from the initial file. The parameters affected by this choice are the ones marked as keep or reset in the table below, in the Common elements update section.

Keep all modified values

The values of the editable parameters that originated from the initial bitstream configuration file will be unaltered. This will ensure that any user modifications are maintained.

Reset all modified values

The values of the editable parameters that originated from the initial bitstream configuration file will be reset to the value found in the new file. All user modifications will be lost.

2. Select the type of refresh and click OK. A pop-up window will appear, listing all the changes and requesting user input on whether or not to apply them.

3. Click Yes then OK to apply the changes. 

4. The configuration can be reset when Bitstream configuration location equals Standard repositories. To do so, choose the option < Select your file > from the drop-down menu containing the available configurations.

Detecting changes in the bitstream configuration file

When updating a bitstream configuration file, a slot is considered common between the old and new .opal files if the slot name is the same and the supported IO card type is compatible; channel groups within these slots are considered common if their names are the same.
A raw data item (as an example an element of the list Data to board or Load from board) is considered common if the same port is used in both files; this applies even if the maximum allowed DWORD count is not the same (the minimum of the two is kept). 
The Remote Boards Configuration is considered common if both files specify support of the MuSE functionality.

These concepts are illustrated in the examples below:

Example 1: 

The old bitstream configuration file defines a digital in card (OP5351) in Slot1A, an analog out card (OP5330-1) in Slot1B and a digital out card in Slot2A.

The new bitstream configuration file defines a digital in card (OP5367-5) in Slot1A, an analog out card (OP5330-3) in Slot1B and an analog in card in Slot2B.

Only Slot1B slot is considered in common :

  • Slot1A: the slot name is the same however the digital in cards in the new and old bitstream configuration files are not compatible (refer to section General Compatibility Rules for Multiple I/O Card Types). When the new bitstream configuration file is applied, the information and configuration of Slot1A will be reset to the values contained in the new .opal.

  • Slot1B: the slot name is the same and the analog out cards in the new and old bitstream configuration files are compatible (refer to section General Compatibility Rules for Multiple I/O Card Types). When the new bitstream configuration file is applied, the Slot1B IO card type is reset to the card type in the new file (OP5330-3), however the user configurations applied on the associated common channel groups will be kept.

  • Slot2A: only available in the old bitstream and will be removed when the new bitstream configuration file is applied.

  • Slot2B: only available in the new bitstream configuration file and will be added to the configuration when the file is applied.



Example 2: 

The old bitstream configuration file contains 2 Data from board items, using ports 0 and 1. Port 0 has a maximum DWORD count of 250, out which the user has configured 4.

The new bitstream configuration file contains 2 Data from board items, using ports 0 and 2. Port 0 has a maximum DWORD count of 2.

The port 0 is in common :

  • Port 0: kept, but only the first 2 previously configured DWORDS remain, as the new maximum DWORD count has changed to 2.

  • Port 1: removed due to not being defined in the new configuration file.

  • Port 2: added according to the new file.

Example 3: 

Both old and new bitstream configuration files specify support of the MuSE feature; the remote boards configured by the user will be kept when loading the new file.

Common elements update

The parameters of the elements that were deemed common to both files according to the constraints explained above can be divided into 3 categories:

  • keep: applies to parameters that did not originate from a bitstream configuration file, such as remote configuration parameters. The values of these parameters will remain unaltered during bitstream configuration file changes.

  • reset: applies to read-only parameters that did originate from a bitstream configuration file, such as the slot description. Their value will be reset to the value found in the new bitstream configuration file.

  • keep or reset: applies to editable parameters that did originate from a bitstream configuration file such as the high and low values for the threshold or the digital channel direction. Their value can be either kept or reset, depending on the user preference.

Common elements

Action

Explanation

Common elements

Action

Explanation



















Slot configuration



Description

reset

The value of the Description field will be reset to the value in the new bitstream configuration file.

Functionality

reset

The Functionality field will be reset to the value in the new bitstream configuration file.

IO card type

reset

The IO card type field will be reset to the value in the new bitstream configuration file.

Analog Inputs

keep

The Analog Inputs channel group configuration (refer to Analog Inputs) is applied to the new configuration.

Analog Outputs

keep

The Analog Outputs channel group configuration (refer to Analog Outputs) is applied to the new configuration.

Digital Inputs

keep

The Digital Inputs channel group configuration (refer to Digital Inputs) is applied to the new configuration.

Digital Output

keep

The Digital Outputs channel group configuration (refer to Digital Outputs) is applied to the new configuration.

Digital In channel group Threshold low value

keep or reset

If a slot contains a card with support for configurable thresholds (refer to section General Compatibility Rules for Multiple I/O Card Types), the Threshold low value from the old configuration is kept or reset according to the user preferences.

Digital In channel group Threshold high value

keep or reset

If a slot contains a card with support for configurable thresholds (refer to section General Compatibility Rules for Multiple I/O Card Types), the Threshold high value from the old configuration is kept or reset according to the user preferences.

Bidirectional channel group Direction

keep or reset

If a slot contains a card supporting configurable direction (refer to section General Compatibility Rules for Multiple I/O Card Types), the Direction is kept or reset according to the user preferences.







Raw data configuration

Raw data from board ports

keep

If both the old and the new bitstream configuration files define the same raw data from board ports, the configuration done (refer to section Raw Data From Board (DataOUT)) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw data to board ports

keep

If both the old and the new bitstream configuration files define the same raw data to board ports, the configuration done (refer to section Raw Data To Board (DataIN)) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw load from board ports

keep

If both the old and the new bitstream configuration files define the same raw load from board ports, the configuration done (refer to section Asynchronous Raw Data From Board (LoadOUT)) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw load to board ports

keep

If both the old and the new bitstream configuration files define the same raw load to board ports, the configuration done (refer to section Asynchronous Raw Data From Board (LoadIN)) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Remote boards configuration



keep

If the MuSE feature is available in both old and new bitstreams, the remote boards configuration (refer to section Remote Board Configuration) will be kept when loading the new bitstream configuration file.





Connections

Once the I/O interface has been configured, the user must connect points in the model to points in the I/O interface. This can be done using the standard HYPERSIM workflow for connections.

The I/O interface connectable points depend on its configuration, namely on the available types of I/O and the number of channels enabled for each I/O board.

For a list of the possible connectable points of each I/O type, refer to its documentation. 

Supported I/O Types

I/O Name

Direction

I/O Name

Direction

Analog In

To model

Analog Out

From model

Digital In 

To model

Digital Out

From model

Raw Data from Board

To model

Raw Data to Board

From model

Asynchronous Raw Data From Board (Load OUT)

To model

Asynchronous Raw Data To Board (Load IN)

From model

Limitations

The current version of the I/O interface has the following limitations:

  • The Disable strict hardware mismatch validation feature is not available on OP5142 (OP5600).

  • On all chassis, FPGA-simulated motor models are not supported at the moment.

  • Chassis type OP5143 standalone is supported only for MuSE as central with four remotes. Using it as MuSE remote is not supported . It does not support any I/Os.

  • The change detection mechanism when the bitstream configuration file is updated in only available when Bitstream configuration location is set to File system.

List of Compatibilities

Chassis and FPGA board

Supported

Chassis and FPGA board

Supported

OP4200 with a MEZX5 module

No

OP4500 with an MMPK7 module

No (platform deprecated)

OP4510 with a TE0741 module 

Yes

OP4512 with a TE0741 module

Yes

OP4520 I/O expansion box with a TE0741 module 

Yes

OP4610 with a TE0741 module

Yes

OP5600 with an OP5142 board 

Yes

OP5600 with an ML605 board 

No (platform deprecated)

OP5650 with an OP5143 board

Yes

OP5607 I/O expansion box with a VC707 board

Yes

OP5707 with a VC707 board

Yes

OP7020 I/O expansion box with a VC707 board

Yes

OP7160/OP7161

No (platform deprecated)

OP7170

Yes

OP5143 Standalone

Yes

Limitations of the Multi-System Expansion Link Feature

Restrictions to using the MuSE link with the software architecture may apply depending on your application and software configuration. To verify compatibility, please contact OPAL-RT's support team.



List of Module Compatibilities for the MuSE feature

Chassis and FPGA board 

Central 

Remote

Chassis and FPGA board 

Central 

Remote

OP4200 with a MEZX5 module

No

Yes

OP4500 with an MMPK7 module 

No

No

OP4510 with a TE0741 module 

Yes

Yes

OP4512 with a TE0741 module

Yes

Yes

OP4520 I/O expansion box with a TE0741 module 

Yes, if connected via PCIe to a simulator

Yes

OP4610 with a TE0741 module

Yes

Yes

OP5600 with an OP5142 board 

Yes

No

OP5600 with an ML605 board

No

No

OP5607 I/O expansion box with a VC707 board 

Yes, if connected via PCIe to a simulator

Yes

OP5700 with a VC707 board 

Yes

Yes

OP7020 I/O expansion box with a VC707 board

Yes, if connected via PCIe to a simulator

Yes

OP7160/OP7161

No

No

OP7170

Yes

Yes

OP5143 Standalone

Yes

No



General Compatibility Rules for Multiple I/O Card Types

I/O card

Type

Description

Compatible with

I/O card

Type

Description

Compatible with

OP5340

AIN

OPAL-RT OP5340 SCMB, 16 ch, 16 bit, 1us, A/D, +-5 V to +- 100V

OP5340; OP5340-2

OP5340-2

AIN

OPAL-RT OP5340-2 SCMB, 8 ch, 16 bit, 1us, A/D, +-5 V to +- 100V

OP5340; OP5340-2

OP5330-1

AOUT

OPAL-RT OP5330-1 SCMB, D/A 16 Ch@35ma Digital to Analog Module

OP5330-1; OP5330-3

OP5330-3

AOUT

OPAL-RT OP5330-3 SCMB, D/A 16 Ch@15ma Digital to Analog Module'

OP5330-1; OP5330-3

OP5351

DIN

OPAL-RT OP5351 TTL Digital Mezzanine - 32 Din

OP5351; OP5353; OP5357; OP5358-3; OP5358-5

OP5353

DIN

OPAL-RT OP5353 Opto-Isolated Digital Mezzanine - 32 Din

OP5351; OP5353; OP5357; OP5358-3; OP5358-5

OP5357

DIN

OPAL-RT OP5357 LVDS Digital Mezzanine - 32 Din

OP5351; OP5353; OP5357; OP5358-3; OP5358-5

OP5358-3

DIN

OPAL-RT OP5358-3 Digital Mezzanine 3V RS422- 32 Din

OP5351; OP5353; OP5357; OP5358-3; OP5358-5

OP5358-5

DIN

OPAL-RT OP5358-5 Digital Mezzanine 5V RS422 - 32 Din

OP5351; OP5353; OP5357; OP5358-3; OP5358-5

OP5352

DOUT

OPAL-RT OP5352 TTL Digital Mezzanine - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5354

DOUT

OPAL-RT OP5354 Opto-Isolated Digital Mezzanine - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5355

DOUT

OPAL-RT OP5355 LVDS Digital Mezzanine - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5356-3

DOUT

OPAL-RT OP5356-3 Digital Mezzanine 3V RS422- 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5356-5

DOUT

OPAL-RT OP5356-5 Digital Mezzanine 5V RS422 - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5359

DOUT

OPAL-RT OP5359 Open-collector Digital Mezzanine - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5360-1

DOUT

OPAL-RT OP5360-1 Digital Mezzanine Push-Pull FET 5 to 15V,  50ns - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3

OP5360-2

DOUT

OPAL-RT OP5360-2 Digital Mezzanine Push-Pull FET 5 to 30V,  65-200ns - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 

OP5360-3

DOUT

OPAL-RT OP5360-3 Digital Mezzanine Push-Pull FET 5 to 30V,  65-200ns CE - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; OP5360-3 

OP5363

DIN

OPAL-RT OP5363 High Impedance Dual Threshold - 32 Din

None

OP5367-1

DOUT

OPAL-RT OP5367 TTL - 32 Dout

None

OP5367-3

DIN / DOUT

OPAL-RT OP5367 configurable threshold / TTL - 16 Din 16 Dout

None

OP5367-5

DIN

OPAL-RT OP5367 configurable threshold - 32 Din

None

OP5369

DIN / DOUT

OPAL-RT OP5369 configurable direction and threshold - 32 ch

None





OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
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