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Block


Table of Contents

Description

The 24-Phase Hysteresis Controller block implements the driver of the FPGA-based 24-Phase Hysteresis Controller. The settings of this parameter panel are transformed into the control signals of the FPGA-based controller.


Mask Parameters

Motor Parameters tab

Back EMF table: [-1:+1]: Normalised back-EMF table. This table must be a vector with the same number of element as the breakpoints vector. The back emf generated voltage will be emf = lambda*we*emf_table(theta_elec)/max(emf_table) volts. This table is just to declare the shape of the back emf during one electrical turn.

Back EMF Breakpoints: [0:360]: Breakpoints of the back EMF table. Only breakpoints between 0 and 360degrees are relevant, out of limit values will be ignored.

Flux linkage: [Vpeak.s/rad]: Flux linkage value or lambda that will set the back emf amplitude (it's equal to the back emf peak amplitude @1rad.s-1 electrical). Note: emf = lambda*we*emf_table(theta_elec)/max(emf_table) volts.

Torque constant: Value of the torque constant Kt. Torque = Kt*lambda*I?emf_table(theta_elec)/max(emf_table).

Number of poles: The number of poles value. It must be an integer number between 0 and 64.

Theta offset for Phase 1 to 24: [deg]: Offset angle value for each phase. It must be a 24 element vector. First value correspond to the first phase angle offset, second corresponds to the second phase and so on, up to the 24th phase.

These values are mainly used for the Emf Voltages generation:

Emf1 = lambda*we*emf_table(theta_elec+offset(1))/max(emf_table)
Emf2 = lambda*we*emf_table(theta_elec+offset(2))/max(emf_table)
...
Emf24 = lambda*we*emf_table(theta_elec+offset(24))/max(emf_table)

Solver Time Step: [sec]: Value in seconds of the solver time step. This value must be contained between 800ns and 5us.

24 Phases / 12 Phases tabs

Inductance Matrix: [H]: Inductance matrix for 24phase and 12phase mode. It must be a 24x24 matrix (24phase mode) or 12x12 matrix (12phase mode).

Phase resistance: [Ohm]: Phase resistance for 24phase and 12phase mode. It can be a 24x24 matrix (24phase mode) or 12x12 matrix (12phase mode) or a scalar value (default for both mode).

Configuration tab

Hardware Controller Name (OpCtrl): Controller Name label of the OpCtrl or OpLnk block which must be linked with this block.

FPGA Clock Period: [sec]: This parameter is locked to the FPGA clock period, which is 5ns by default.

Configuration Port Numbers: Port number of the various configuration ports used within by this block. These port numbers are specific to the FPGA firmware version. Please check the bitstream documentation to know these port numbers.


Inputs

Speed: Speed of the motor in RPM (mechanical speed). The user can force the speed or use an external mechanical equation to feedback the speed processed from the torque output.

Force_v: The user has the ability to over-ride the voltage coming from the inverter with the force_v input and specify his own voltages. Set to 1 will override the inverter voltages with the v_forced value.

v_forced: The forced voltage, used only if the Force_v is set to 1.

12ph_mode_sel: This port can be use to select which source drives the series switch of the motor. Set to 0, the Digital Inputs drives the series switch. Set to 1, the 12ph_mode input from the block drives the series switches.

12ph_mode: The 12ph_mode input is used to activate the series switches and use the motor in 12 phases mode. This inport is activated only if the 12ph_mode_sel input is set to 1 (or a higher value). Otherwise, the motor mode will be set by the Inputs dedicated to the series switches.

Rst: The rst port is useful in case of solver instability due to wrong block parameters. A value higher than one activates the solver reset.


Outputs

Imot: The 24-phase currents

mec_angle: The motor mechanical angle.

elec_angle: The motor electrical angle.

torque: The motor electrical torque.

emf1: The back-EMF voltage of the phase 1.

spare_out: This output is used for debug purposes only.

comm_status: This output port gives the communication port to/from the FPGA status.

running: The Running port tells if the solver is ready to use or not. When 0, the solver is initialising or in reset mode. When 1 the solver is up and running.


Characteristics and limitations

Models that include this block should be provided with a detailed description document. Refer to this document to obtain more information about the block specifications.

Direct FeedthroughNO
Discrete sample timeYES
XHP supportYES
Work offlineNO


If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

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