Description

This block implements a signal mapping and rescaling interface to send up to 32 SFP signals from 8 FLWS model serial signal links and 1 Data In link from the CPU.

The transfer can be triggered by either an internal synchronization signal, or any of the 8 input FLWS links last signal.

Inputs

externalSync: This input must be a Bool signal. It should be a pulse train whose period is equal to the sample time requested for the SFP output channels. Refer to the Hardware documentation for the minimum sampling time of the interface.

LoadIn, LoadInSof: This loadin port is to receive mapping, gain, offset and synchronisation configuration from CPU.

DataIn, DataInSof: This datain port is used for transfering real time channels from the CPU.

Model Signal Serial {1..8}: These inputs are providing the FPGA signals that could be mapped to the SFP output channels. They have to follow the OPAL-RT FLWS Protocol. Inner data size is 32 bits (i.e XFloat8_24), any additional bit would be discarded. Each input can transport a maximum of 128 channels. As an example, this signal could be provided by the eHS (Gen4 onwards) or a machine model. The SFP channels transfer can be triggered by any of these input links by using the right Synchronisation source configuration from the LoadIn port.

Outputs

Frame: This output to stream up to 32 channels from any mapped channel of the 8 input FLWS serial channels or the data in channels. The transfer is triggered depending on the triggering source selected by the block configuration. 

Reset: This output is the signal used to reset the block. If reset is applied, data coming out of the frame outport should be discarded.

Configured: This output is 1 until the next reset if the SFP has been configured through loadin. 

Characteristics and limitations

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.