Description

This block performs the control of the 2 resolvers and 2 Quadrature Encoders embeded in the FPGA Dual angle sensor with faults module.

It also communicates with the FPGA in order to monitor the resolver signals and the sensor angle.

Mask Parameters

General tab

Set all parameters from input ports: When selected, all other parameters will be disabled from the block mask and corresponding input ports will appear for dynamic access during the real-time simulation. Numerical value to send to the input port for the popup menus is written between square brackets in the description below.

Resolver {i} Carrier Source: This parameter selects the resolver carrier source, between the internal carrier generator [1] or an external source (generally from an analog input channel) [0].

Resolver {i} Carrier Frequency: Internal carrier generator frequency, in hertz.

Resolver {i} Pole Pairs: Number of pole pairs of the resolver/encoder emulator. This parameter should be an integer number between 0 and 63.

Resolver {i} Angle Offset: Offset apply to the rotor angle in degrees to adjust the phase of the resolver/encoder angle. This parameter is applied before the resolver/encoder pole pair parameter.

Resolver {i} Reverse Speed: When selected [1], this option reverse the resolver sine/cosine modulation direction

Encoder {i} Resolution: The quadrature encoder resolution, in pulses per revolution.

Encoder {i} Polarity: This parameter sets the encoder polarity, Active-High [1] or Active-Low [0].

Show fault settings : When this option is selected, parameters for fault control will appear in the block mask.

Resolver {i} Sine Modulator Sine Gain: The sine modulation output sine component amplitude. Default value is 1.

Resolver {i} Sine Modulator Cosine Gain: The sine modulation output cosine component amplitude. Default value is 0.

Resolver {i} Cosine Modulator Sine Gain: The cosine modulation output sine component amplitude. Default value is 0.

Resolver {i} Cosine Modulator Cosine Gain: The cosine modulation output cosine component amplitude. Default value is 1.

Configuration tab

Communication port numbers: Number of the communication port used to communicate with the FPGA core. Please check the bitstream documentation to setup accordingly this tab.

Controller Name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Inputs

The input ports description is equivalent to the parameter description above.

Outputs

Resolver[i]Out: This output is a Simulink composite signal containing all outputs from the resolvers and encoders emulated by the block.These signals are:

• Theta_sensor: Angle of the resolver/encoder pair as received from the Theta (i) input.
• sin_res, cos_res, car_res: The resolver sine modulation, cosine modulation and carrier, respectively.

Characteristics and limitations

This block has no special characteristics.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.