Power and Reset Push Button with LED indicator:
- Normal press: Power On or shut down the unit.
- Long press: If the button is pressed for at least 4 seconds, the unit will shut down.
- Integrated LED
  - Green: The unit is On
  - Black (unlit): The unit is Off
Small form-factor pluggable (SFP) module connectors: Provide high-speed communication links between other FPGA simulators or third-party devices.
Each socket controls one communication link.
CH00 through CH03 are reserved to expand an OPAL-RT’s simulator I/O capability using OPAL-RT’s Multi-System Expansion link (MuSE). NOTE: Feature available in Q1-2025.
CH04 through CH11 are compatible with the legacy generic Aurora link.
SFP transceivers and fiber-optic cables must be selected (and purchased separately) according to the type and speed of the communication protocol.
Note: MuSE link requires specific SFP transceivers and optical fiber cables:
- SFP: Avago AFBR-57R5APZ
- Cable: LC-LC multimode 850 nm optical fiber

The LEDs associated with the selected channel will light to indicate the channel is selected.
LEDs are arrow-shaped to indicate the channels to which they are associated.

The LED upward arrow points to the top channel
The LED downward arrow points to the bottom channel (see below)

Green:
- ON: SFP is inserted
- OFF: No SFP is present
- BLINKING: Channel active
Red:
- OFF: Connection OK
- ON: transmission fault
- BLINKING: Reception loss

Ethernet ports at 1 Gb/s
Only the lower Ethernet port identified “1” is supported. The upper port identified “0” is not used.
LED link status is described in the table below.

Status	Green LED	Yellow LED
No link	Off	Off
Link - No Activity	Solid On	Solid On
Link - Activity	Blink	Solid On

TX/RX Fiber-Optic Connectors (square connectors):
- Synchronizes time steps between systems and includes high-speed FPGA pulses
- Compatible with OPAL-RT XG series of real-time simulators: OP4610XG, OP5033XG, OP5705XG, and OP5707XG.
IRIG-B or 1PPS (future use)
USB port for JTAG programming
FPGA status LED indicators:
- POWER: Unit is On and all internal power are correct
- STATUS: FPGA status
  - Solid green: User bitstream FPGA is programmed
  - Blink green: Safe bitstream FPGA is programmed
  - Off: FPGA programming error
- SYNC: Synchronization status
  - Solid green: RX and TX synchronization are OK
  - Blink green: RX and TX synchronization are OK, but timestep is very long
  - Off: No synchronization
- USER: User-defined LED
  - Can be programmed to solid green, blinking green or off
LCD screen change page button
- Press the button to display the next page
- When the last page is displayed, it returns to the first page
LCD screen: Display information on different pages:
- The screen displays 4 lines of 20 characters

Page	Information displayed	Example
Boot page	Model number Serial number
ID page	Chassis name: Defined by the user in RT-LAB and HYPERSIM hosts. IP address: The IP address is required to flash the bitstream and the unit need to be connected to the network via Ethernet. At system boot, the IP address is assigned as follows: The unit will wait for 10 seconds to receive an IP address offered from a DHCP server and use it. If the unit did not receive an IP address from a DHCP server, it will use an internal configured IP address, the default one being 192.168.3.5. Chassis ID: an ID number defined by the customer at purchase and programmed at factory assembly by OPAL-RT. It can be changed afterward, as explained below.
Network page	MAC addresses: Only MAC address 1 (MAC1) is used at the moment
Status page	Simulation status: IDLE: Simulation in idle mode LOADING: Simulation is loading RUNNING: Simulation is running STOPPED: Simulation is stopped PAUSED: Simulation is paused
Software version	Device firmware version

Changing the Chassis ID Number

Remove the front panel as explained in this page.

Set the dip switches SW2 in binary code on 8-bit to change the chassis ID number.
- Range is between 0 and 255.
- Switch down is 0 and switch up is 1

OP4810-IO/OP4815-IO - Front Interface

Changing the Chassis ID Number